Inventor
Chuanbin Pan
Inventor
San Jose, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices24%
H10NElectric solid-state devices not otherwise provided for20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests15%
H01LSemiconductor devices10%
H10DInorganic electric semiconductor devices7%
G11CStatic stores5%
G06FElectric digital data processing2%
PatentTitleYear
11,126,517Method and system for communication channels to management controller20219,806,256'Resistive memory device having sidewall spacer electrode and method of making thereof'20178,987,119'Pillar devices and methods of making thereof'20158,981,331'Memory cells having storage elements that share material layers with steering elements and methods of forming the same'20158,969,845'Memory cells having storage elements that share material layers with steering elements and methods of forming the same'20158,592,793'Electrode diffusions in two-terminal non-volatile memory devices'20138,450,181'In-situ passivation methods to improve performance of polysilicon diode'20138,389,971'Memory cells having storage elements that share material layers with steering elements and methods of forming the same'20137,955,981'Method of making a two-terminal non-volatile memory pillar device with rounded corner'20117,906,392'Pillar devices and methods of making thereof'20117,723,180'Multilevel nonvolatile memory device containing a carbon storage material and methods of making and using same'20106,309,956'Fabricating low K dielectric interconnect systems by using dummy structures to enhance process'20016,154,366'Structures and processes for fabricating moisture resistant chip-on-flex packages'20006,143,647'Silicon-rich block copolymers to achieve unbalanced vias'20006,051,869'Silicon-rich block copolymers to achieve unbalanced vias'20006,037,249'Method for forming air gaps for advanced interconnect systems'20006,027,995'Method for fabricating an interconnect structure with hard mask and low dielectric constant materials'20005,886,410'Interconnect structure with hard mask and low dielectric constant materials'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2001Patents assigned to INTEL CORP (7)· patent assignee history
1999–2000Based in Santa Clara, CA, US· patent location history
2000–2017Based in San Jose, CA, US· patent location history
2010–2015Patents assigned to SANDISK 3D LLC (9)· patent assignee history
2013–2015Patents assigned to PAN CHUANBIN (4)· patent assignee history
2013Patents assigned to CHEN XIYING (2)· patent assignee history
2013Patents assigned to CHEN YUNG-TIN (2)· patent assignee history
2013–2015Based in Sunnyvale, CA, US· patent location history
2021Based in Taoyuan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK 3D LLC | 9 | 2010–2015 |
| INTEL CORP | 7 | 1999–2001 |
| PAN CHUANBINself | 4 | 2013–2015 |
| CHEN XIYING | 2 | 2013 |
| CHEN YUNG-TIN | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 10 | 2000–2017 |
| Santa Clara, California, US | 4 | 1999–2000 |
| Sunnyvale, California, US | 3 | 2013–2015 |
| Taoyuan, TW | 1 | 2021 |