Inventor
Bradley G. Burgess
Inventor
Austin, TX, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
G11CStatic stores8%
H03KPulse technique4%
H10DInorganic electric semiconductor devices4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
9,836,304Cumulative confidence fetch throttling20179,588,770'Dynamic rename based register reconfiguration of a vector register file'20179,424,041'Efficient way to cancel speculative ‘source ready’ in scheduler for direct and nested dependent instructions'20169,395,988'Micro-ops including packed source and destination fields'20168,736,308'Pipeline power gating'20147,921,293'Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment'20117,024,555'Apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment'20066,950,904'Cache way replacement technique'20056,519,683'System and method for instruction cache re-ordering'20036,477,640'Apparatus and method for predicting multiple branches and performing out-of-order branch resolution'20026,202,130'Data processing system for processing vector data and method therefor'20016,157,999'Data processing system having a synchronizing link stack and method thereof'20006,157,998'Method for performing branch prediction and resolution of two or more branch instructions within two or more branch prediction buffers'20005,642,493'Method of loading instructions into an instruction cache by repetitively using a routine containing a mispredicted branch instruction'19975,500,943'Data processor with rename buffer and FIFO buffer for in-order instruction completion'19965,448,744'Integrated circuit microprocessor with programmable chip select logic'19955,408,428'Programmable bit cell'19955,392,228'Result normalizer and method of operation'19955,361,392'Digital computing system with low power mode and special bus cycle therefor'19945,329,621'Microprocessor which optimizes bus utilization based upon bus speed'19945,072,365'Direct memory access controller using prioritized interrupts for varying bus mastership'19915,034,922'Intelligent electrically erasable, programmable read-only memory with improved read latency'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2002Patents assigned to MOTOROLA INC (13)· patent assignee history
1991–2017Based in Austin, TX, US· patent location history
2003–2011Patents assigned to INTEL CORP (4)· patent assignee history
2014–2017Patents assigned to ADVANCED MICRO DEVICES INC (2)· patent assignee history
2016–2017Patents assigned to SAMSUNG ELECTRONICS CO LTD (3)· patent assignee history
2017Patents assigned to BURGESS BRADLEY GENE (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MOTOROLA INC | 13 | 1991–2002 |
| INTEL CORP | 4 | 2003–2011 |
| SAMSUNG ELECTRONICS CO LTD | 3 | 2016–2017 |
| ADVANCED MICRO DEVICES INC | 2 | 2014–2017 |
| BURGESS BRADLEY GENEself | 2 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 22 | 1991–2017 |