Inventor
Andre Schaefer
Inventor
Braunschweig, DE
Overview
Patents· 37 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
G06FElectric digital data processing11%
H01LSemiconductor devices9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
H10BElectronic memory devices4%
H10DInorganic electric semiconductor devices4%
G05FSystems for regulating electric or magnetic variables3%
H01FMagnets3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
PatentTitleYear
10,851,516Shaft cover for shafts, channel entrances, or drainage channels202010,853,216Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems202010,079,489Power management in multi-die assemblies20189,921,640'Integrated voltage regulators with magnetically enhanced inductors'20189,911,689'Through-body-via isolated coaxial capacitor and techniques for forming same'20189,768,148'Stacked memory with interface providing offset interconnects'20179,472,249'Techniques for accessing a dynamic random access memory array'20169,391,453'Power management in multi-die assemblies'20169,361,970'Configuration for power reduction in DRAM'20169,311,983'Dynamically applying refresh overcharge voltage to extend refresh cycle time'20169,287,196'Resonant clocking for three-dimensional stacked devices'20169,263,422'Interlayer communications for 3D integrated circuit stack'20169,230,614'Separate microchannel voltage domains in stacked memory architecture'20169,229,466'Fully integrated voltage regulators for multi-stack integrated circuit architectures'20169,135,982'Techniques for accessing a dynamic random access memory array'20159,086,881'Mechanism for facilitating write tracking for following data eye movements across changing thermal conditions in memory systems'20159,087,559'Memory sense amplifier voltage modulation'20159,026,767'Adaptive address mapping with dynamic runtime memory mapping selection'20159,000,577'Interlayer communications for 3D integrated circuit stack'20158,971,087'Stacked memory with interface providing offset interconnects'20158,959,271'System and method for accessing memory'20158,811,110'Configuration for power reduction in DRAM'20148,547,769'Energy efficient power distribution for 3D integrated circuit stack'20138,321,719'Efficient clocking scheme for a bidirectional data link'20128,135,936'Adaptive address mapping with dynamic runtime memory mapping selection'20128,037,375'Fast data eye retraining for a memory'20117,587,655'Method of transferring signals between a memory device and a memory controller'20097,355,921'Device in a memory circuit for definition of waiting times'20087,321,240'Driver circuit for binary signals'20087,180,805'Differental current source for generating DRAM refresh signal'20077,068,079'Circuit device with clock pulse detection facility'20067,049,930'Arrangement of several resistors jointly positioned in a well of a semiconductor device, and a semiconductor device including at least one such arrangement'20066,917,562'Semi-conductor component with clock relaying device'20056,911,732'Integrated circuit'20056,783,596'Wafer handling device'20046,690,612'Voltage supply for semiconductor memory'20046,625,065'Method for masking DQ bits'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2009Patents assigned to INFINEON TECHNOLOGIES AG (11)· patent assignee history
2003–2004Based in Mnchen, DE· patent location history
2005–2008Based in Munich, DE· patent location history
2008–2009Based in München, DE· patent location history
2011–2020Patents assigned to INTEL CORP (25)· patent assignee history
2011–2020Based in Braunschweig, DE· patent location history
2012–2016Patents assigned to SCHAEFER ANDRE (11)· patent assignee history
2012–2015Patents assigned to GRIES MATTHIAS (2)· patent assignee history
2013–2016Patents assigned to SARASWAT RUCHIR (3)· patent assignee history
2016–2018Based in Sassenburg, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 25 | 2011–2020 |
| INFINEON TECHNOLOGIES AG | 11 | 2003–2009 |
| SCHAEFER ANDREself | 11 | 2012–2016 |
| SARASWAT RUCHIR | 3 | 2013–2016 |
| GRIES MATTHIAS | 2 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Braunschweig, DE | 22 | 2011–2020 |
| Munich, DE | 6 | 2005–2008 |
| Mnchen, DE | 3 | 2003–2004 |
| Sassenburg, DE | 2 | 2016–2018 |
| München, DE | 2 | 2008–2009 |