Inventor

Gavin J. Stark

Inventor

Cambridge, GB

Overview

1999–2020

Patent span

Physics

Primary field (CPC G)

Patents· 114 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing48%

H04LTransmission of digital information, e.g. telegraphic communication39%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%

H03KPulse technique2%

H04BTransmission2%

G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy1%

G11CStatic stores1%

H04QSelecting1%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%

Y10TTechnical subjects covered by former us classification1%

PatentTitleYear

10,853,074Table fetch processor instruction using table number to base address translation2020 10,659,030Transactional memory that performs a statistics add-and-update operation2020 10,474,465Pop stack absolute instruction2019 10,365,681Multiprocessor system having fast clocking prefetch circuits that cause processor clock signals to be gapped2019 10,366,019Multiprocessor system having efficient and shared atomic metering resource2019 10,362,093NFA completion notification2019 10,228,968Network interface device that alerts a monitoring processor if configuration of a virtual NID is changed2019 10,230,638Executing a selected sequence of instructions depending on packet type in an exact-match flow switch2019 10,191,867Multiprocessor system having posted transaction bus interface that generates posted transaction bus commands2019 10,146,468Addressless merge command with data item identifier2018 10,031,755Kick-started run-to-completion processing method that does not involve an instruction counter2018 10,031,878Configurable mesh data bus in an island-based network flow processor2018 10,033,638Executing a selected sequence of instructions depending on packet type in an exact-match flow switch2018 10,031,754Kick-started run-to-completion processor having no instruction counter2018 10,009,270Modular and partitioned SDN switch2018 9,998,374Method of handling SDN protocol messages in a modular and partitioned SDN switch2018 9,971,720Distributed credit FIFO link of a configurable mesh data bus2018 9,940,097Registered FIFO2018 9,912,591'Flow switch IC that uses flow IDs and an exact-match flow table'2018 9,900,090'Inter-packet interval prediction learning algorithm'2018 9,899,996'Recursive lookup with a hardware trie structure that has no sequential logic elements'2018 9,887,918'Intelligent packet data register file that stalls picoengine and retrieves data from a larger buffer'2018 9,866,480'Hash range lookup command'2018 9,854,072Script-controlled egress packet modifier2017 9,846,662Chained CPP command2017 9,830,153Skip instruction to skip a number of instructions on a predicate2017 9,819,585'Making a flow ID for an exact-match flow table using a programmable reduce table circuit'2017 9,804,959'In-flight packet processing'2017 9,804,976'Transactional memory that performs an atomic look-up, add and lock operation'2017 9,807,006'Crossbar and an egress packet modifier in an exact-match flow switch'2017 9,756,152'Making a flow ID for an exact-match flow table using a byte-wide multiplexer circuit'2017 9,753,725'Picoengine having a hash generator with remainder input S-box nonlinearizing'2017 9,753,883'Network interface device that maps host bus writes of configuration information for virtual NIDs into a small transactional memory'2017 9,753,710'Resource allocation with hierarchical scope'2017 9,729,353'Command-driven NFA hardware engine that encodes multiple automatons'2017 9,729,442'Method of detecting large flows within a switch fabric of an SDN switch'2017 9,727,499'Hardware first come first serve arbiter using multiple request buckets'2017 9,703,739'Return available PPI credits command'2017 9,699,084'Forwarding messages within a switch fabric of an SDN switch'2017 9,699,107'Packet engine that uses PPI addressing'2017 9,678,866'Transactional memory that supports put and get ring commands'2017 9,665,519'Using a credits available value in determining whether to issue a PPI allocation request to a packet engine'2017 9,641,436'Generating a flow ID by passing packet data serially through two CCT circuits'2017 9,626,306'Global event chain in an island-based network flow processor'2017 9,619,418'Local event ring in an island-based network flow processor'2017 9,621,481'Configurable mesh control bus in an island-based network flow processor'2017 9,612,841'Slice-based intelligent packet data register file'2017 9,612,981'Configurable mesh data bus in an island-based network flow processor'2017 9,584,637'Guaranteed in-order packet delivery'2017 9,577,832'Generating a hash using S-box nonlinearizing of a remainder input'2017 9,558,224'Automaton hardware engine employing memory-efficient transition table indexing'2017 9,559,988'PPI allocation request and response for accessing a memory system'2017 9,548,947'PPI de-allocate CPP bus command'2017 9,535,851'Transactional memory that performs a programmable address translation if a DAT bit in a transactional memory write command is set'2017 9,519,484'Picoengine instruction that controls an intelligent packet data register file prefetch function'2016 9,519,482'Efficient conditional instruction having companion load predicate bits instruction'2016 9,503,372'SDN protocol message handling within a modular and partitioned SDN switch'2016 9,495,158'Multi-processor system having tripwire data merging and collision detection'2016 9,489,202'Processor having a tripwire bus port and executing a tripwire instruction'2016 9,489,337'Picoengine multi-processor with task assignment'2016 9,483,439'Picoengine multi-processor with power control management'2016 9,467,378'Method of generating subflow entries in an SDN switch'2016 9,465,651'Transactional memory having local CAM and NFA resources'2016 9,450,890'Pipelined egress packet modifier'2016 9,417,916'Intelligent packet data register file that prefetches data for future instruction execution'2016 9,417,656'NFA byte detector'2016 9,417,844'Storing an entropy signal from a self-timed logic bit stream generator in an entropy storage ring'2016 9,413,665'CPP bus transaction value having a PAM/LAM selection code field'2016 9,405,713'Commonality of memory island interface and structure'2016 9,401,880'Flow control using a local event ring in an island-based network flow processor'2016 9,389,908'Transactional memory that performs a TCAM 32-bit lookup operation'2016 9,385,957'Flow key lookup involving multiple simultaneous cam operations to identify hash values in a hash bucket'2016 9,348,778'Transactional memory that performs an ALUT 32-bit lookup operation'2016 9,344,384'Inter-packet interval prediction operating algorithm'2016 9,342,313'Transactional memory that supports a get from one of a set of rings command'2016 9,330,041'Staggered island structure in an island-based network flow processor'2016 9,311,004'Transactional memory that performs a PMM 32-bit lookup operation'2016 9,298,495'Transactional memory that performs an atomic metering command'2016 9,282,051'Credit-based resource allocator circuit'2016 9,280,297'Transactional memory that supports a put with low priority ring command'2016 9,268,600'Picoengine pool transactional memory architecture'2016 9,262,136'Allocate instruction and API call that contain a sybmol for a non-memory resource'2016 9,237,095'Island-based network flow processor integrated circuit'2016 9,223,555'Hierarchical resource pools in a linker'2015 9,176,905'Recursive use of multiple hardware lookup structures in a transactional memory'2015 9,164,730'Self-timed logic bit stream generator with command to run for a number of state transitions'2015 9,164,794'Hardware prefix reduction circuit'2015 9,152,452'Transactional memory that performs a CAMR 32-bit lookup operation'2015 9,146,920'Transactional memory that performs an atomic look-up, add and lock operation'2015 9,124,644'Script-controlled egress packet modifier'2015 9,098,353'Transactional memory that performs a split 32-bit lookup operation'2015 9,100,212'Transactional memory that performs a direct 32-bit lookup operation'2015 9,098,264'Transactional memory that performs a direct 24-BIT lookup operation'2015 9,092,284'Entropy storage ring having stages with feedback inputs'2015 9,069,603'Transactional memory that performs an atomic metering command'2015 9,069,602'Transactional memory that supports put and get ring commands'2015 9,069,649'Distributed credit FIFO link of a configurable mesh data bus'2015 9,069,558'Recursive use of multiple hardware lookup structures in a transactional memory'2015 9,071,545'Network appliance that determines what processor to send a future packet to based on a predicted future arrival time'2015 9,042,252'Inter-packet interval prediction learning algorithm'2015 8,972,630'Transactional memory that supports a put with low priority ring command'2015 8,972,668'Transactional memory that performs an ALUT 32-bit lookup operation'2015 8,930,675'Transactional memory that performs a TCAM 32-bit lookup operation'2015 8,930,639'Transactional memory that performs a PPM 32-bit lookup operation'2015 8,929,376'Flow control using a local event ring in an island-based network flow processor'2015 8,930,872'Staggered island structure in an island-based network flow processor'2015 8,908,693'Flow key lookup involving multiple simultaneous cam operations to identify hash values in a hash bucket'2014 8,902,902'Recursive lookup with a hardware trie structure that has no sequential logic elements'2014 8,793,438'Atomic compare and write memory'2014 8,775,686'Transactional memory that performs an atomic metering command'2014 8,559,436'Processing resource management in an island-based network flow processor'2013 7,007,156'Multiple coprocessor architecture to process a plurality of subtasks in parallel'2006 6,963,535'MAC bus interface'2005 5,953,336'Method and apparatus for source rate pacing in an ATM network'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2020Based in Cambridge, GB· patent location history

2005–2006Based in Fremont, CA, US· patent location history

2013–2020Patents assigned to NETRONOME SYSTEMS INC (111)· patent assignee history

2013–2017Patents assigned to STARK GAVIN J (28)· patent assignee history

2013–2016Patents assigned to ZAGORIANAKOS STEVEN W (5)· patent assignee history

2013–2015Patents assigned to SWARTZENTRUBER RON L (3)· patent assignee history

2014–2016Patents assigned to NEUGEBAUER ROLF (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
NETRONOME SYSTEMS INC	111	2013–2020
STARK GAVIN Jself	28	2013–2017
ZAGORIANAKOS STEVEN W	5	2013–2016
NEUGEBAUER ROLF	3	2014–2016
SWARTZENTRUBER RON L	3	2013–2015

Locations

Location	Patents	Span
Cambridge, GB	112	1999–2020
Fremont, California, US	2	2005–2006