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Inventor

Sarvesh Bhardwaj

Inventor
Fremont, CA, US

Overview

4→
Patents
2009–2014
Patent span
Physics
Primary field (CPC G)

Patents· 4 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
8,813,011'Clock-reconvergence pessimism removal in hierarchical static timing analysis'20148,775,855'Reducing memory used to store totals in static timing analysis'20148,434,040'Clock-reconvergence pessimism removal in hierarchical static timing analysis'20137,630,852'Method of evaluating integrated circuit system performance using orthogonal polynomials'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009Based in Tempe, AZ, US· patent location history
2013–2014Patents assigned to SYNOPSYS INC (3)· patent assignee history
2013–2014Patents assigned to BHARDWAJ SARVESH (2)· patent assignee history
2013–2014Patents assigned to KUCUKCAKAR KAYHAN (2)· patent assignee history
2013–2014Patents assigned to RAHMAT KHALID (2)· patent assignee history
2013–2014Based in Fremont, CA, US· patent location history
2014Patents assigned to HELAIHEL RACHID (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SYNOPSYS INC32013–2014
BHARDWAJ SARVESHself22013–2014
KUCUKCAKAR KAYHAN22013–2014
RAHMAT KHALID22013–2014
HELAIHEL RACHID12014
Locations
LocationPatentsSpan
Fremont, California, US32013–2014
Tempe, AZ, US12009