Inventor
Guillermo J. Rozas
Inventor
Los Gatos, CA, US
Overview
Patents· 93 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing87%
H03KPulse technique3%
G11CStatic stores2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H03MCoding1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
PatentTitleYear
10,761,748Future write in distributed system maintaining data storage integrity202010,540,283Coherence de-coupling buffer202010,387,253System and method to utilize larger block sizes for logical disk and further decompose into smaller physical block sizes for redundant encoding by utilizing erasure coding201910,234,893Dual-domain dynamic multiplexer and method of transitioning between asynchronous voltage and frequency domains201910,108,424Profiling code portions to generate translations201810,102,142Virtual address based memory reordering201810,061,582Method for increasing the speed of speculative execution20189,891,972'Lazy runahead operation for a microprocessor'20189,875,105Checkpointed buffer for re-entry from runahead20189,824,009'Information coherency maintenance systems and methods'20179,823,931'Queued instruction re-dispatch after runahead'20179,804,854'Branching to alternate code based on runahead determination'20179,740,553'Managing potentially invalid results during runahead'20179,652,244'Processing bypass directory tracking system and method'20179,645,929'Speculative permission acquisition for shared memory'20179,632,976'Lazy runahead operation for a microprocessor'20179,582,280'Branching to alternate code based on runahead determination'20179,569,214'Execution pipeline data forwarding'20179,558,116'Coherence de-coupling buffer'20179,552,208'System, method, and computer program product for remapping registers based on a change in execution mode'20179,547,602'Translation lookaside buffer entry systems and methods'20179,411,595'Multi-threaded transactional memory coherence'20169,367,467'System and method for managing cache replacements'20169,323,315'Method and system for automatic clock-gating of a clock grid at a clock source'20169,081,563'Method and apparatus for enhancing scheduling in an advanced microprocessor'20158,924,648'Method and system for caching attribute data for matching attributes with physical addresses'20148,898,395'Memory management for cache consistency'20148,751,753'Coherence de-coupling buffer'20148,677,106'Unanimous branch instructions in a parallel thread processor'20148,656,214'Dual ported replicated data cache'20148,650,555'Method for increasing the speed of speculative execution'20148,615,646'Unanimous branch instructions in a parallel thread processor'20138,572,355'Support for non-local returns in parallel thread SIMD engine'20138,566,564'Method and system for caching attribute data for matching attributes with physical addresses'20138,522,253'Hardware support for virtual machine and operating system context switching in translation lookaside buffers and virtually tagged caches'20138,508,262'Signal generator with output frequency greater than the oscillator frequency'20138,464,033'Setting a flag bit to defer event handling to one of multiple safe points in an instruction stream'20138,438,548'Consistency checking of source instruction to execute previously translated instructions between copy made upon occurrence of write operation to memory and current version'20138,413,162'Multi-threading based on rollback'20138,370,604'Method and system for caching attribute data for matching attributes with physical addresses'20138,239,656'System and method for identifying TLB entries associated with a physical address of a specified range'20128,209,517'Method and apparatus for enhancing scheduling in an advanced microprocessor'20128,209,518'Processing bypass directory tracking system and method'20128,035,430'Signal generator with output frequency greater than the oscillator frequency'20118,019,983'Setting a flag bit to defer event handling to a safe point in an instruction stream'20117,979,669'Method and system for caching attribute data for matching attributes with physical addresses'20117,971,002'Maintaining instruction coherency in a translation-based computer system architecture'20117,937,566'Processing bypass directory tracking system and method'20117,937,536'Handling direct memory accesses'20117,913,058'System and method for identifying TLB entries associated with a physical address of a specified range'20117,904,789'Techniques for detecting and correcting errors in a memory device'20117,904,891'Checking for instruction invariance to execute previously obtained translation code by comparing instruction to a copy stored when write operation to the memory portion occur'20117,873,793'Supporting speculative modification in a data cache'20117,840,788'Checking for exception by floating point instruction reordered across branch by comparing current status in FP status register against last status copied in shadow register'20107,793,347'Method and system for validating a computer system'20107,747,896'Dual ported replicated data cache'20107,734,892'Memory protection and address translation hardware support for virtual machines'20107,725,656'Braided set associative caching techniques'20107,724,027'Method and system for elastic signal pipelining'20107,725,677'Method and apparatus for improving segmented memory addressing'20107,696,797'Signal generator with output frequency greater than the oscillator frequency'20107,646,835'Method and system for automatically calibrating intra-cycle timing relationships for sampling signals for an integrated circuit device'20107,636,815'System and method for handling direct memory accesses'20097,634,635'Systems and methods for reordering processor instructions'20097,620,779'System and method for handling direct memory accesses'20097,606,997'Method and system for using one or more address bits and an instruction to increase an instruction set'20097,606,979'Method and system for conservatively managing store capacity available to a processor issuing stores'20097,478,226'Processing bypass directory tracking system and method'20097,404,181'Switching to original code comparison of modifiable code for translated code validity when frequency of detecting memory overwrites exceeds threshold'20087,380,096'System and method for identifying TLB entries associated with a physical address of a specified range'20087,380,098'Method and system for caching attribute data for matching attributes with physical addresses'20087,376,798'Memory management methods and systems that support cache consistency'20087,337,307'Exception handling with inserted status check command accommodating floating point instruction forward move across branch'20087,337,439'Method for increasing the speed of speculative execution'20087,334,109'Method and apparatus for improving segmented memory addressing'20087,310,723'Methods and systems employing a flag for deferring exception handling to a commit or rollback point'20077,249,246'Methods and systems for maintaining information for locating non-native processor instructions when executing native processor instructions'20077,225,299'Supporting speculative modification in a data cache'20077,149,872'System and method for identifying TLB entries associated with a physical address of a specified range'20067,149,851'Method and system for conservatively managing store capacity available to a processor issuing stores'20067,096,460'Switching to original modifiable instruction copy comparison check to validate prior translation when translated sub-area protection exception slows down operation'20067,089,404'Method and apparatus for enhancing scheduling in an advanced microprocessor'20067,089,397'Method and system for caching attribute data for matching attributes with physical addresses'20066,851,040'Method and apparatus for improving segmented memory addressing'20056,826,682'Floating point exception handling in pipelined processor using special instruction to detect generated exception and execute instructions singly from known correct state'20046,748,589'Method for increasing the speed of speculative execution'20046,738,893'Method and apparatus for scheduling to reduce space and increase speed of microprocessor operations'20046,725,361'Method and apparatus for emulating a floating point stack in a translation process'20046,594,821'Translation consistency checking for modified target instructions by comparing to original copy'20036,470,339'Resource access control in a software system'20026,370,639'Processor architecture having two or more floating-point status fields'20026,205,466'Infrastructure for an open digital services marketplace'20016,151,669'Methods and apparatus for efficient control of floating-point status register'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2020Based in Los Gatos, CA, US· patent location history
2001–2002Based in Mountain View, CA, US· patent location history
2003–2009Patents assigned to TRANSMETA CORP (22)· patent assignee history
2009–2018Patents assigned to ROZAS GUILLERMO J (26)· patent assignee history
2009–2017Patents assigned to ROZAS GUILLERMO (16)· patent assignee history
2009–2017Patents assigned to KLAIBER ALEXANDER (14)· patent assignee history
2013–2019Patents assigned to NVIDIA CORP (21)· patent assignee history
2016–2019Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ROZAS GUILLERMO Jself | 26 | 2009–2018 |
| TRANSMETA CORP | 22 | 2003–2009 |
| NVIDIA CORP | 21 | 2013–2019 |
| ROZAS GUILLERMOself | 16 | 2009–2017 |
| KLAIBER ALEXANDER | 14 | 2009–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 89 | 2000–2020 |
| Santa Clara, California, US | 2 | 2016–2019 |
| Mountain View, California, US | 2 | 2001–2002 |