Inventor
Ramnath Venkatraman
Inventor
San Jose, CA, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%
G11CStatic stores18%
H10BElectronic memory devices18%
H10DInorganic electric semiconductor devices16%
G06FElectric digital data processing9%
H03KPulse technique9%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G05FSystems for regulating electric or magnetic variables1%
H03HImpedance networks, e.g. resonant circuits1%
PatentTitleYear
9,158,319'Closed-loop adaptive voltage scaling for integrated circuits'20158,738,940'Power controller for SoC power gating applications'20148,624,352'Mitigation of detrimental breakdown of a high dielectric constant metal-insulator-metal capacitor in a capacitor bank'20148,589,853'Total power optimization for a logic integrated circuit'20138,429,586'Basic cell architecture for structured ASICs'20138,411,399'Defectivity-immune technique of implementing MIM-based decoupling capacitors'20138,178,909'Integrated circuit cell architecture configurable for memory or logic elements'20128,166,440'Basic cell architecture for structured application-specific integrated circuits'20128,112,734'Optimization with adaptive body biasing'20128,044,437'Integrated circuit cell architecture configurable for memory or logic elements'20117,869,251'SRAM based one-time-programmable memory'20117,440,356'Modular design of multiport memory bitcells'20087,404,154'Basic cell architecture for structured application-specific integrated circuits'20087,304,874'Compact ternary and binary CAM bitcell architecture with no enclosed diffusion areas'20077,082,067'Circuit for verifying the write speed of SRAM cells'20067,069,535'Optical proximity correction method using weighted priorities'20067,042,747'Ternary CAM bitcells'20067,006,370'Memory cell architecture'20067,006,369'Design and use of a spacer cell to support reconfigurable memories'20066,980,462'Memory cell architecture for reduced routing congestion'20056,934,174'Reconfigurable memory arrays'20056,828,653'Method of forming metal fuses in CMOS processes with copper interconnect'20046,806,551'Fuse construction for integrated circuit structure having low dielectric constant dielectric material'20046,713,381'Method of forming semiconductor device including interconnect barrier layers'20046,664,141'Method of forming metal fuses in CMOS processes with copper interconnect'20036,566,171'Fuse construction for integrated circuit structure having low dielectric constant dielectric material'20036,442,061'Single channel four transistor SRAM'20026,218,302'Method for forming a semiconductor device'20016,174,810'Copper interconnect structure and method of formation'20016,093,966'Semiconductor device with a copper barrier layer and formation thereof'20006,077,768'Process for fabricating a multilevel interconnect'20005,814,557'Method of forming an interconnect structure'19985,783,485'Process for fabricating a metallized interconnect'19985,677,244'Method of alloying an interconnect structure with copper'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2004Patents assigned to MOTOROLA INC (8)· patent assignee history
1997–2004Based in Austin, TX, US· patent location history
2002–2011Patents assigned to LSI LOGIC CORP (13)· patent assignee history
2002–2015Based in San Jose, CA, US· patent location history
2007–2015Patents assigned to LSI CORP (13)· patent assignee history
2012–2014Patents assigned to VENKATRAMAN RAMNATH (8)· patent assignee history
2012–2014Patents assigned to CASTAGNETTI RUGGERO (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI CORP | 13 | 2007–2015 |
| LSI LOGIC CORP | 13 | 2002–2011 |
| MOTOROLA INC | 8 | 1997–2004 |
| VENKATRAMAN RAMNATHself | 8 | 2012–2014 |
| CASTAGNETTI RUGGERO | 4 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 26 | 2002–2015 |
| Austin, Texas, US | 8 | 1997–2004 |