Inventor
Tsung-Yuan Yu
Inventor
Taipei, TW
Overview
Patents· 78 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H01LSemiconductor devices36%
H10DInorganic electric semiconductor devices11%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
G06FElectric digital data processing2%
H05KPrinted circuits1%
Y10TTechnical subjects covered by former us classification1%
G01CMeasuring distances, levels or bearings1%
G06NComputing arrangements based on specific computational models1%
G06TImage data processing or generation, in general1%
PatentTitleYear
11,057,606Method and display system for information display based on positions of human gaze and object202110,811,369Packaging devices and methods of manufacture thereof202010,720,495Semiconductor device and manufacturing method thereof202010,714,442Interconnect structures and methods of forming same202010,522,480Packaging devices and methods of manufacture thereof201910,510,652Method of manufacturing semiconductor device201910,475,760Semiconductor device201910,312,204System and method for an improved interconnect structure201910,269,904Semiconductor structure and manufacturing method thereof201910,262,964Interconnect structures and methods of forming same201910,079,213Packaging devices and methods of manufacture thereof201810,043,770System and method for an improved interconnect structure201810,037,962Ball height control in bonding process20189,997,480Method of forming a semiconductor device including strain reduced structure20189,997,483Ball amount process in the manufacturing of integrated circuit20189,984,965Inductor system and method20189,978,704Semiconductor devices with ball strength improvement20189,935,070Interconnect structures and methods of forming same20189,831,196Methods and apparatus of guard rings for wafer-level-packaging20179,831,205Semiconductor device and manufacturing method thereof20179,812,392'Inductor system and method'20179,806,042'Strain reduced structure for IC packaging'20179,786,591'Capacitor in post-passivation structures and methods of forming the same'20179,679,868'Ball height control in bonding process'20179,673,160'Packaging devices, methods of manufacture thereof, and packaging methods'20179,647,054'Inductor system and method'20179,633,963'Packaging devices and methods of manufacture thereof'20179,633,870'System and method for an improved interconnect structure'20179,589,915'Semiconductor device and manufacturing method thereof'20179,589,862'Interconnect structures and methods of forming same'20179,559,067'Methods and apparatus of guard rings for wafer-level-packaging'20179,553,045'Inductor for post passivation interconnect and a method of forming'20179,530,759'3D package with through substrate vias'20169,490,203'Capacitor in post-passivation structures and methods of forming the same'20169,449,927'Seal ring structure with metal-insulator-metal capacitor'20169,443,812'Semiconductor device with post-passivation interconnect structure and method of forming the same'20169,437,739'Finfet seal ring'20169,437,567'Semiconductor devices with ball strength improvement'20169,437,490'Semiconductor device and manufacturing method thereof'20169,406,739'Inductor system and method'20169,401,308'Packaging devices, methods of manufacture thereof, and packaging methods'20169,397,056'Semiconductor device having trench adjacent to receiving area and method of forming the same'20169,396,973'Methods and apparatus for wafer level packaging'20169,379,076'Semiconductor device and manufacturing method thereof'20169,379,067'Semiconductor devices and methods of manufacture thereof having guard ring structure'20169,368,417'Contact test structure and method'20169,362,243'Semiconductor package device and forming the same'20169,355,978'Packaging devices and methods of manufacture thereof'20169,355,954'Capacitor in post-passivation structures and methods of forming the same'20169,355,906'Packaging devices and methods of manufacture thereof'20169,349,665'Methods and apparatus of packaging of semiconductor devices'20169,337,154'Semiconductor device and method of manufacturing the same'20169,337,117'Chip package and method of manufacturing the same'20169,305,877'3D package with through substrate vias'20169,287,143'Apparatus for package reinforcement using molding underfill'20169,275,925'System and method for an improved interconnect structure'20169,269,682'Method of forming bump structure'20169,269,658'Ball amount process in the manufacturing of integrated circuit'20169,257,333'Interconnect structures and methods of forming same'20169,245,842'Semiconductor devices having guard ring structure and methods of manufacture thereof'20169,136,318'Capacitor in post-passivation structures and methods of forming the same'20159,129,816'Contact test structure and method'20159,117,831'Seal ring structure for integrated circuit chips'20159,099,485'Methods and apparatus of guard rings for wafer-level-packaging'20159,013,038'Semiconductor device with post-passivation interconnect structure and method of forming the same'20159,006,891'Method of making a semiconductor device having a post-passivation interconnect structure'20159,000,876'Inductor for post passivation interconnect'20158,994,181'Bond pad structure to reduce bond pad corrosion'20158,987,922'Methods and apparatus for wafer level packaging'20158,957,503'Chip package and method of manufacturing the same'20158,916,465'UBM structures for wafer level chip scale packaging'20148,884,400'Capacitor in Post-Passivation structures and methods of forming the same'20148,871,629'Methods of and semiconductor devices with ball strength improvement'20148,692,378'UBM structures for wafer level chip scale packaging'20148,624,359'Wafer level chip scale package and method of manufacturing the same'20148,581,389'Uniformity control for IC passivation structure'20138,581,400'Post-passivation interconnect structure'20138,217,499'Structure to reduce etching residue'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (37)· patent assignee history
2012–2017Patents assigned to CHEN HSIEN-WEI (12)· patent assignee history
2012–2017Patents assigned to YU TSUNG-YUAN (12)· patent assignee history
2012–2020Based in Taipei, TW· patent location history
2013–2017Patents assigned to CHEN YING-JU (7)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (40)· patent assignee history
2016Based in Hsinchu, TW· patent location history
2021Based in Kaohsiung, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 40 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 37 | 2012–2016 |
| CHEN HSIEN-WEI | 12 | 2012–2017 |
| YU TSUNG-YUANself | 12 | 2012–2017 |
| CHEN YING-JU | 7 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taipei, TW | 76 | 2012–2020 |
| Kaohsiung, TW | 1 | 2021 |
| Hsinchu, TW | 1 | 2016 |