Inventor
Mu-Jing Li
Inventor
Sunnyvale, CA, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing85%
F16CShafts3%
G05BControl or regulating systems in general3%
G06VImage or video recognition or understanding3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y02PClimate change mitigation technologies in the production or processing of goods3%
PatentTitleYear
9,569,517'Fault tolerant distributed key-value storage'20179,230,049'Arraying power grid vias by tile cells'20168,984,449'Dynamically generating jog patches for jog violations'20158,891,878'Method for representing images using quantized embeddings of scale-invariant image features'20148,719,756'Power grid mosaicing with deep-sub-tile cells'20148,645,453'Method and system of processing cookies across domains'20148,423,943'Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow'20138,117,581'Self-propelling decoupling capacitor design for flexible area decoupling capacitor fill design flow'20127,519,929'Method and computer program product for interlayer connection of arbitrarily complex shapes under asymmetric via enclosure rules'20097,380,227'Automated correction of asymmetric enclosure rule violations in a design layout'20087,096,447'Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout'20067,007,258'Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout'20066,915,252'Method and system for ensuring consistency of design rule application in a CAD environment'20056,895,568'Correction of spacing violations between pure fill via areas in a multi-wide object class design layout'20056,892,368'Patching technique for correction of minimum area and jog design rule violations'20056,892,363'Correction of width violations of dummy geometries'20056,883,149'Via enclosure rule check in a multi-wide object class design layout'20056,871,332'Structure and method for separating geometries in a design layout into multi-wide object classes'20056,832,360'Pure fill via area extraction in a multi-wide object class design layout'20046,816,998'Correction of spacing violations between dummy geometries and wide class objects of design geometries'20046,804,808'Redundant via rule check in a multi-wide object class design layout'20046,792,586'Correction of spacing violations between wide class objects of dummy geometries'20046,775,806'Method, system and computer product to produce a computer-generated integrated circuit design'20046,772,401'Correction of spacing violations between design geometries and wide class objects of dummy geometries'20046,769,099'Method to simplify and speed up design rule/electrical rule checks'20046,735,749'(Design rule check)/(electrical rule check) algorithms using a system resolution'20046,718,527'Automated design rule violation correction when adding dummy geometries to a design layout'20046,637,013'Method and system for automating design rule check error correction in a CAD environment'20036,608,335'Grounded fill in a large scale integrated circuit'20036,499,135'Computer aided design flow to locate grounded fill in a large scale integrated circuit'20026,323,614'System and method for controlling suspension using a magnetic field'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2009Patents assigned to SUN MICROSYSTEMS INC (22)· patent assignee history
2002–2015Based in Sunnyvale, CA, US· patent location history
2012–2014Patents assigned to LI MU-JING (3)· patent assignee history
2012–2013Patents assigned to ORACLE AMERICA INC (2)· patent assignee history
2012–2016Based in Santa Clara, CA, US· patent location history
2014–2016Patents assigned to ORACLE INT CORP (3)· patent assignee history
2014Patents assigned to LI MU (2)· patent assignee history
2014Based in State College, PA, US· patent location history
2014Based in Hangzhou, CN· patent location history
2017Based in Pittsburgh, PA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SUN MICROSYSTEMS INC | 22 | 2002–2009 |
| LI MU-JINGself | 3 | 2012–2014 |
| ORACLE INT CORP | 3 | 2014–2016 |
| LI MUself | 2 | 2014 |
| ORACLE AMERICA INC | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 23 | 2002–2015 |
| Santa Clara, California, US | 4 | 2012–2016 |
| Pittsburgh, Pennsylvania, US | 1 | 2017 |
| State College, Pennsylvania, US | 1 | 2014 |
| Hangzhou, CN | 1 | 2014 |