Inventor

Runzi Chang

Inventor

San Jose, CA, US

Overview

2010–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 50 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices19%

H10BElectronic memory devices16%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

H10DInorganic electric semiconductor devices12%

H10NElectric solid-state devices not otherwise provided for11%

G11CStatic stores10%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%

G06FElectric digital data processing3%

Y02PClimate change mitigation technologies in the production or processing of goods2%

Y10TTechnical subjects covered by former us classification2%

PatentTitleYear

10,854,455Methods and apparatus for fabricating IC chips with tilted patterning2020 10,784,167Isolation components for transistors formed on fin features of semiconductor substrates2020 10,784,250Sub-device field-effect transistor architecture for integrated circuits2020 10,713,411Photolithography mask design-rule check assistance2020 10,707,411MRAM structure for efficient manufacturability2020 10,672,861Memory chip design for manufacturing2020 10,600,793Fabricating memory devices with optimized gate oxide thickness2020 10,535,774Modular memory-like layout for finFET analog designs2020 10,522,394Method of creating aligned vias in ultra-high density integrated circuits2019 10,431,574Methods and systems for packaging semiconductor devices to improve yield2019 10,319,727Fabricating memory devices with optimized gate oxide thickness2019 10,217,669Isolation components for transistors formed on fin features of semiconductor substrates2019 10,056,363Methods and systems to improve yield in multiple chips integration processes2018 10,037,400Integrated circuit manufacturing process for aligning threshold voltages of transistors2018 9,768,144'Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate'2017 9,490,427'Resistive random access memory cell structure'2016 9,397,218'Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices'2016 9,391,045'Recessed semiconductor substrates and associated techniques'2016 9,275,985'RC networks that include an integrated high resistance resistor on top of a MOS capacitor'2016 9,275,731'Systems and methods for increasing the read sensitivity of a resistive random access memory (RRAM)'2016 9,257,410'Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrate'2016 9,245,961'Reducing source contact to gate spacing to decrease transistor pitch'2016 9,214,230'Resistive random access memory cell structure with reduced programming voltage'2015 9,147,837'Resistive memory cell and method for forming a resistive memory cell'2015 9,142,445'Method and apparatus for forming shallow trench isolation structures having rounded corners'2015 9,129,678'Method and apparatus for reforming a memory cell of a memory'2015 9,112,133'Resistive random access memory and method for controlling manufacturing of corresponding sub-resolution features of conductive and resistive elements'2015 9,047,945'Systems and methods for reading resistive random access memory (RRAM) cells'2015 9,042,159'Configuring resistive random access memory (RRAM) array for write operations'2015 9,034,730'Recessed semiconductor substrates and associated techniques'2015 8,999,786'Reducing source contact to gate spacing to decrease transistor pitch'2015 8,993,398'Method for creating ultra-high-density holes and metallization'2015 8,947,909'System and method for creating a bipolar resistive RAM (RRAM)'2015 8,934,285'Method and apparatus for forming a contact in a cell of a resistive random access memory to reduce a voltage required to program the cell'2015 8,885,388'Apparatus and method for reforming resistive memory cells'2014 8,873,309'Apparatus and method for repairing resistive memories and increasing overall read sensitivity of sense amplifiers'2014 8,609,528'High-density patterning'2013 8,241,993'Method for shallow trench isolation'2012 8,030,215'Method for creating ultra-high-density holes and metallization'2011 8,030,128'Method to form high density phase change memory (PCM) top contact every two bits'2011 7,994,052'High-density patterning'2011 7,985,616'Methods to form wide heater trenches and to form memory cells to engage heaters'2011 7,939,414'Ion implantation and process sequence to form smaller base pick-up'2011 7,939,445'High density via and metal interconnect structures, and methods of forming the same'2011 7,892,936'Self aligned integration of high density phase change memory with thin film access device'2011 7,888,166'Method to form high efficiency GST cell using a double heater cut'2011 7,863,709'Low base resistance bipolar junction transistor array'2011 7,807,539'Ion implantation and process sequence to form smaller base pick-up'2010 7,745,809'Ultra high density phase change memory having improved emitter contacts, improved GST cell reliability and highly matched UHD GST cells using column mirco-trench strips'2010 7,709,835'Method to form high efficiency GST cell using a double heater cut'2010

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2010–2020Patents assigned to MARVELL WORLD TRADE LTD (28)· patent assignee history

2010–2020Patents assigned to MARVELL INT LTD (22)· patent assignee history

2010–2020Based in San Jose, CA, US· patent location history

2010–2015Based in Santa Clara, CA, US· patent location history

2012–2016Patents assigned to CHANG RUNZI (7)· patent assignee history

2012–2016Patents assigned to WU ALBERT (5)· patent assignee history

2020Patents assigned to MARVELL ASIA PTE LTD (4)· patent assignee history

2020Based in Saratoga, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MARVELL WORLD TRADE LTD	28	2010–2020
MARVELL INT LTD	22	2010–2020
CHANG RUNZIself	7	2012–2016
WU ALBERT	5	2012–2016
MARVELL ASIA PTE LTD	4	2020

Locations

Location	Patents	Span
San Jose, California, US	45	2010–2020
Santa Clara, California, US	4	2010–2015
Saratoga, California, US	1	2020