Inventor
Janet Wang
Inventor
San Francisco, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores47%
H10DInorganic electric semiconductor devices20%
H10BElectronic memory devices17%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests13%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
PatentTitleYear
6,618,290'Method of programming a non-volatile memory cell using a baking process'20036,590,811'Higher program VT and faster programming rates based on improved erase methods'20036,567,303'Charge injection'20036,555,436'Simultaneous formation of charge storage and bitline to wordline isolation'20036,541,816'Planar structure for non-volatile memory devices'20036,490,205'Method of erasing a non-volatile memory cell using a substrate bias'20026,468,865'Method of simultaneous formation of bitline isolation and periphery oxide'20026,465,306'Simultaneous formation of charge storage and bitline to wordline isolation'20026,465,303'Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory'20026,459,618'Method of programming a non-volatile memory cell using a drain bias'20026,456,531'Method of drain avalanche programming of a non-volatile memory cell'20026,456,533'Higher program VT and faster programming rates based on improved erase methods'20026,456,536'Method of programming a non-volatile memory cell using a substrate bias'20026,410,956'Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices'20026,331,952'Positive gate erasure for non-volatile memory cells'20016,331,953'Intelligent ramped gate and ramped drain erasure for non-volatile memory cells'20016,269,023'Method of programming a non-volatile memory cell using a current limiter'20016,266,281'Method of erasing non-volatile memory cells'20016,233,175'Self-limiting multi-level programming states'20016,188,101'Flash EPROM cell with reduced short channel effect and method for providing same'20016,172,909'Ramped gate technique for soft programming to tighten the Vt distribution'20016,025,240'Method and system for using a spacer to offset implant damage and reduce lateral diffusion in flash memory devices'20005,888,867'Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Patents assigned to ADVANCED MICRO DEVICES INC (23)· patent assignee history
1999–2003Based in San Francisco, CA, US· patent location history
2002–2003Patents assigned to FUJITSU LTD (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 23 | 1999–2003 |
| FUJITSU LTD | 4 | 2002–2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Francisco, California, US | 23 | 1999–2003 |