Inventor
Clarence W. DeKarske
Inventor
St. Paul Park, MN, US
Overview
Patents· 7 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing60%
G11CStatic stores30%
H04JMultiplex communication10%
PatentTitleYear
4,984,153'Storage locking control for a plurality of processors which share a common storage unit'19914,945,512'High-speed partitioned set associative cache memory'19904,930,106'Dual cache RAM for rapid invalidation'19904,595,911'Programmable data reformat system'19864,560,939'Synchronized selectable rate clocking system'19854,556,978'Error checked high speed shift matrix'19854,168,541'Paired least recently used block replacement system'1979Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1979Patents assigned to SPERRY RAND CORP (1)· patent assignee history
1979–1991Based in St. Paul Park, MN, US· patent location history
1985–1986Patents assigned to SPERRY CORP (3)· patent assignee history
1985Based in St. Paul, MN, US· patent location history
1990–1991Patents assigned to UNISYS CORP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPERRY CORP | 3 | 1985–1986 |
| UNISYS CORP | 3 | 1990–1991 |
| SPERRY RAND CORP | 1 | 1979 |
Locations
| Location | Patents | Span |
|---|---|---|
| St. Paul Park, Minnesota, US | 6 | 1979–1991 |
| St. Paul, Minnesota, US | 1 | 1985 |