Inventor
Shih-Kuang Chiu
Inventor
Taichung, TW
Overview
Patents· 43 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H01LSemiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
B81BMicrostructural devices or systems, e.g. micromechanical devices9%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems8%
H10DInorganic electric semiconductor devices4%
H05KPrinted circuits3%
Y02PClimate change mitigation technologies in the production or processing of goods2%
A44BButtons, pins, buckles, slide fasteners, or the like1%
A44DIndexing scheme relating to buttons, pins, buckles or slide fasteners, and to jewellery, bracelets or other personal adornments1%
PatentTitleYear
10,772,390Buckle device202010,615,055Method for fabricating package structure202010,199,239Package structure and fabrication method thereof201910,049,955Fabrication method of wafer level packaging semiconductor package with sandwich structure of support plate isolation layer and bonding layer20189,991,178Interposer and electrical testing method thereof20189,899,237'Carrier, semiconductor package and fabrication method thereof'20189,899,308'Semiconductor package and method of fabricating the same'20189,875,981Semiconductor device having conductive vias20189,812,340'Method of fabricating semiconductor package having semiconductor element'20179,659,806'Semiconductor package having conductive pillars'20179,607,939'Semiconductor package and method of fabricating the same'20179,520,304'Semiconductor package and fabrication method thereof'20169,502,333'Semiconductor device having conductive vias'20169,487,393'Fabrication method of wafer level package having a pressure sensor'20169,425,119'Package structure and fabrication method thereof'20169,324,585'Semiconductor package and method of fabricating the same'20169,133,021'Wafer level package having a pressure sensor and fabrication method thereof'20159,117,698'Fabrication method of semiconductor package'20159,041,189'Semiconductor package and method of fabricating the same'20158,829,672'Semiconductor package, package structure and fabrication method thereof'20148,741,693'Method for manufacturing package structure with micro-electromechanical element'20148,680,692'Carrier, semiconductor package and fabrication method thereof'20148,653,661'Package having MEMS element and fabrication method thereof'20148,633,048'Method for fabricating package structure having MEMS elements'20148,610,272'Package structure with micro-electromechanical element and manufacturing method thereof'20138,399,940'Package structure having MEMS elements and fabrication method thereof'20138,334,174'Chip scale package and fabrication method thereof'20128,288,189'Package structure having MEMS element and fabrication method thereof'20128,154,115'Package structure having MEMS element and fabrication method thereof'20127,485,496'Semiconductor device package with a heat sink and method for fabricating the same'20096,856,015'Semiconductor package with heat sink'20056,787,918'Substrate structure of flip chip package'20046,692,629'Flip-chip bumbing method for fabricating solder bumps on semiconductor wafer'20046,600,232'Flip-chip semiconductor package structure and process for fabricating the same'20036,506,626'Semiconductor package structure with heat-dissipation stiffener and method of fabricating the same'20036,498,054'Method of underfilling a flip-chip semiconductor device'20026,489,180'Flip-chip packaging process utilizing no-flow underfill technique'20026,459,144'Flip chip semiconductor package'20026,404,064'Flip-chip bonding structure on substrate for flip-chip package application'20026,396,156'Flip-chip bonding structure with stress-buffering property and method for making the same'20026,391,682'Method of performing flip-chip underfill in a wire-bonded chip-on-chip ball-grid array integrated circuit package module'20026,391,683'Flip-chip semiconductor package structure and process for fabricating the same'20026,348,740'Bump structure with dopants'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to SILICONWARE PRECISION INDUSTRIES CO LTD (42)· patent assignee history
2002–2020Based in Taichung, TW· patent location history
2012–2015Patents assigned to CHIU SHIH-KUANG (10)· patent assignee history
2012–2015Patents assigned to LIAO HSIN-YI (7)· patent assignee history
2012–2015Patents assigned to HUANG CHUN-AN (3)· patent assignee history
2013–2015Patents assigned to CHANG HONG-DA (3)· patent assignee history
2020Based in Kaohsiung, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SILICONWARE PRECISION INDUSTRIES CO LTD | 42 | 2002–2020 |
| CHIU SHIH-KUANGself | 10 | 2012–2015 |
| LIAO HSIN-YI | 7 | 2012–2015 |
| CHANG HONG-DA | 3 | 2013–2015 |
| HUANG CHUN-AN | 3 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taichung, TW | 42 | 2002–2020 |
| Kaohsiung, TW | 1 | 2020 |