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Inventor

Robert M. Rassel

Inventor
Colchester, VT, US

Overview

112→
Patents
2006–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 112 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices55%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H01LSemiconductor devices5%
G06FElectric digital data processing4%
H01CResistors3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
Y10TTechnical subjects covered by former us classification2%
H01FMagnets1%
H04NPictorial communication, e.g. television1%
PatentTitleYear
9,412,736'Embedding semiconductor devices in silicon-on-insulator wafers connected using through silicon vias'20169,406,562'Integrated circuit and design structure having reduced through silicon via-induced stress'20169,257,324'Forming structures on resistive substrates'20169,087,925'Si and SiGeC on a buried oxide layer on a substrate'20159,041,105'Integrated circuit including transistor structure on depleted silicon-on-insulator, related method and design structure'20158,921,172'Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure'20148,912,597'Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure'20148,881,379'Method of making heat sink for integrated circuit devices'20148,872,281'Silicided trench contact to buried conductive layer'20148,871,600'Schottky barrier diodes with a guard ring formed by selective epitaxy'20148,809,155'Back-end-of-line metal-oxide-semiconductor varactors'20148,809,998'Semiconductor device including in wafer inductors, related method and design structure'20148,779,476'Asymmetric wedge JFET, related method and design structure'20148,754,455'Junction field effect transistor structure with P-type silicon germanium or silicon germanium carbide gate(s) and method of forming the structure'20148,735,986'Forming structures on resistive substrates'20148,709,855'Intralevel conductive light shield'20148,674,423'Semiconductor structure having vias and high density capacitors'20148,618,588'Anti-blooming pixel sensor cell with active neutral density filter, methods of manufacture, and design structure'20138,618,583'Junction gate field effect transistor structure having n-channel'20138,609,505'Method of forming MIM capacitor structure in FEOL'20138,592,293'Schottky barrier diodes for millimeter wave SiGe BiCMOS applications'20138,519,478'Schottky barrier diode, a method of forming the diode and a design structure for the diode'20138,518,782'Semiconductor device including asymmetric lightly doped drain (LDD) region, related method and design structure'20138,492,843'Lateral hyperabrupt junction varactor diode in an SOI substrate'20138,481,380'Asymmetric wedge JFET, related method and design structure'20138,466,501'Asymmetric silicon-on-insulator (SOI) junction field effect transistor (JFET) and a method of forming the asymmetrical SOI JFET'20138,435,864'Process for single and multiple level metal-insulator-metal integration with a single mask'20138,421,181'Schottky barrier diode with perimeter capacitance well junction'20138,390,038'MIM capacitor and method of making same'20138,338,265'Silicided trench contact to buried conductive layer'20128,299,558'Self-aligned Schottky diode'20128,299,475'Interlevel conductive light shield'20128,288,244'Lateral passive device having dual annular electrodes'20128,242,584'Structure and method to create stress trench'20128,232,139'Integrated structures of high performance active devices and passive devices'20128,230,586'Method of cooling a resistor'20128,216,890'Lateral hyperabrupt junction varactor diode in an SOI substrate'20128,217,497'FIN differential MOS varactor diode'20128,207,568'Process for single and multiple level metal-insulator-metal integration with a single mask'20128,188,591'Integrated structures of high performance active devices and passive devices'20128,169,007'Asymmetric junction field effect transistor'20128,168,500'Double gate depletion mode MOSFET'20128,171,435'Integrated circuit structure incorporating an inductor, an associated design method and an associated design system'20128,163,612'Silicon germanium heterostructure barrier varactor'20128,159,040'Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor'20128,158,988'Interlevel conductive light shield'20128,138,579'Structures and methods of forming SiGe and SiGeC buried layer for SOI/SiGe technology'20128,125,013'Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors'20128,125,049'MIM capacitor structure in FEOL and related method'20128,110,862'Semiconductor structure including trench capacitor and trench resistor'20128,105,924'Deep trench based far subcollector reachthrough'20128,101,494'Structure, design structure and method of manufacturing a structure having VIAS and high density capacitors'20128,035,190'Semiconductor devices'20118,022,496'Semiconductor structure and method of manufacture'20118,015,538'Design structure with a deep sub-collector, a reach-through structure and trench isolation'20118,008,748'Deep trench varactors'20118,008,142'Self-aligned Schottky diode'20117,994,895'Heat sink for integrated circuit devices'20117,989,302'Methods of forming a hyper-abrupt P-N junction and design structures for an integrated circuit'20117,989,306'Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate'20117,977,714'Wrapped gate junction field effect transistor'20117,943,445'Asymmetric junction field effect transistor'20117,936,041'Schottky barrier diodes for millimeter wave SiGe BICMOS applications'20117,919,830'Method and structure for ballast resistor'20117,915,134'Method of integration of a MIM capacitor with a lower plate of metal gate material formed on an STI region or a silicide region formed in or on the surface of a doped well with a high K dielectric material'20117,910,450'Method of fabricating a precision buried resistor'20117,902,606'Double gate depletion mode MOSFET'20117,868,423'Optimized device isolation'20117,829,452'Terminal pad structures and methods of fabricating same'20107,825,441'Junction field effect transistor with a hyperabrupt junction'20107,821,097'Lateral passive device having dual annular electrodes'20107,812,388'Deep trench capacitor and method of making same'20107,804,119'Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit'20107,755,161'Semiconductor devices'20107,750,408'Integrated circuit structure incorporating an inductor, a conductive sheet and a protection circuit'20107,739,636'Design structure incorporating semiconductor device structures that shield a bond pad from electrical noise'20107,718,481'Semiconductor structure and method of manufacture'20107,714,412'MOS varactor using isolation well'20107,700,453'Method for forming hyper-abrupt junction varactors'20107,696,604'Silicon germanium heterostructure barrier varactor'20107,694,262'Deep trench capacitor and method of making same'20107,692,271'Differential junction varactor'20107,691,734'Deep trench based far subcollector reachthrough'20107,691,717'Polysilicon containing resistor with enhanced sheet resistance precision and method for fabrication thereof'20107,670,889'Structure and method for fabrication JFET in CMOS'20107,659,176'Tunable temperature coefficient of resistance resistors and method of fabricating same'20107,582,949'Semiconductor devices'20097,560,761'Semiconductor structure including trench capacitor and trench resistor'20097,545,007'MOS varactor with segmented gate doping'20097,538,409'Semiconductor devices'20097,518,215'One mask hyperabrupt junction varactor using a compensated cathode contact'20097,494,912'Terminal pad structures and methods of fabricating same'20097,491,632'Buried subcollector for high frequency passive semiconductor devices'20097,488,643'MIM capacitor and method of making same'20097,479,439'Semiconductor-insulator-silicide capacitor'20097,397,087'FEOL/MEOL metal resistor for high end CMOS'20087,393,701'Method of adjusting buried resistor resistance'20087,381,997'Lateral silicided diodes'20087,361,993'Terminal pad structures and methods of fabricating same'20087,361,950'Integration of a MIM capacitor with a plate formed in a well region and with a high-k dielectric'20087,335,927'Lateral silicided diodes'20087,329,940'Semiconductor structure and method of manufacture'20087,310,036'Heat sink for integrated circuit devices'20077,285,472'Low tolerance polysilicon resistor for low temperature silicide processing'20077,253,073'Structure and method for hyper-abrupt junction varactors'20077,242,071'Semiconductor structure'20077,239,006'Resistor tuning'20077,217,981'Tunable temperature coefficient of resistance resistors and method of fabricating same'20077,183,628'Structure and method of hyper-abrupt junction varactors'20077,112,535'Precision polysilicon resistor process'20067,098,521'Reduced guard ring in schottky barrier diode structure'20067,060,612'Method of adjusting resistors post silicide process'2006

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2006–2016Patents assigned to IBM (110)· patent assignee history
2006–2016Based in Colchester, VT, US· patent location history
2011Based in Cochester, VT, US· patent location history
2012–2016Patents assigned to RASSEL ROBERT M (44)· patent assignee history
2012–2014Patents assigned to HE ZHONG-XIANG (10)· patent assignee history
2012–2014Patents assigned to COOLBAUGH DOUGLAS D (9)· patent assignee history
2012–2014Patents assigned to ESHUN EBENEZER E (8)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1102006–2016
RASSEL ROBERT Mself442012–2016
HE ZHONG-XIANG102012–2014
COOLBAUGH DOUGLAS D92012–2014
ESHUN EBENEZER E82012–2014
Locations
LocationPatentsSpan
Colchester, VT, US1112006–2016
Cochester, VT, US12011