Inventor
Masanori Tsutsumi
Inventor
Yokkaichi, JP
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices26%
H10BElectronic memory devices26%
H10DInorganic electric semiconductor devices21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
G11CStatic stores2%
H03HImpedance networks, e.g. resonant circuits2%
F01NGas-flow silencers or exhaust apparatus for machines or engines in general1%
G01RMeasuring electric variables1%
H01PWaveguides1%
PatentTitleYear
10,957,680Semiconductor die stacking using vertical interconnection by through-dielectric via structures and methods for making the same202110,903,222Three-dimensional memory device containing a carbon-doped source contact layer and methods for making the same202110,903,232Three-dimensional memory devices containing memory stack structures with laterally separated charge storage elements and method of making thereof202110,861,869Three-dimensional memory device having a slimmed aluminum oxide blocking dielectric and method of making same202010,748,927Three-dimensional memory device with drain-select-level isolation structures and method of making the same202010,748,925Three-dimensional memory device containing channels with laterally pegged dielectric cores202010,559,582Three-dimensional memory device containing source contact to bottom of vertical channels and method of making the same202010,453,798Three-dimensional memory device with gated contact via structures and method of making thereof201910,236,300On-pitch drain select level isolation structure for three-dimensional memory device and method of making the same201910,192,878Three-dimensional memory device with self-aligned multi-level drain select gate electrodes201910,141,331Three-dimensional memory device containing support pillars underneath a retro-stepped dielectric material and method of making thereof201810,083,982Three-dimensional memory device having select gate electrode that is thicker than word lines and method of making thereof20189,991,277Three-dimensional memory device with discrete self-aligned charge storage elements and method of making thereof20189,871,500'Multilayer electronic component'20189,812,463'Three-dimensional memory device containing vertically isolated charge storage regions and method of making thereof'20179,780,034'Three-dimensional memory device containing annular etch-stop spacer and method of making thereof'20179,754,956'Uniform thickness blocking dielectric portions in a three-dimensional memory structure'20179,754,820'Three-dimensional memory device containing an aluminum oxide etch stop layer for backside contact structure and method of making thereof'20179,716,105'Three-dimensional memory device with different thickness insulating layers and method of making thereof'20179,666,594'Multi-charge region memory cells for a vertical NAND device'20179,576,967'Method of suppressing epitaxial growth in support openings and three-dimensional memory device containing non-epitaxial support pillars in the support openings'20179,530,787'Batch contacts for multiple electrically conductive layers'20169,413,328'Diplexer including two bandpass filters'20169,305,937'Bottom recess process for an outer blocking dielectric layer inside a memory opening'20169,305,849'Method of making a three dimensional NAND device'20167,892,969'Method of manufacturing semiconductor device'20117,786,513'Semiconductor integrated circuit device and power source wiring method therefor'20107,456,478'MOS transistor circuit'20087,227,211'Decoupling capacitors and semiconductor integrated circuit'20077,202,725'Delay control circuit device, and a semiconductor integrated circuit device and a delay control method using said delay control circuit device'20076,818,929'Standard cell for plural power supplies and related technologies'20046,810,340'Electromagnetic disturbance analysis method and apparatus and semiconductor device manufacturing method using the method'20044,924,669'Cover structure for exhaust manifold inlet ducts'1990Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2007Patents assigned to MATSUSHITA ELECTRIC INDUSTRIAL CO LTD (4)· patent assignee history
2004–2010Based in Kyoto, JP· patent location history
2007–2008Based in Nishikamo-gun, JP· patent location history
2008–2010Patents assigned to PANASONIC CORP (2)· patent assignee history
2011Based in Kawasaki, JP· patent location history
2016–2021Patents assigned to SANDISK TECHNOLOGIES LLC (21)· patent assignee history
2016–2017Patents assigned to SANDISK TECHNOLOGIES INC (6)· patent assignee history
2016–2018Patents assigned to TDK CORP (2)· patent assignee history
2016–2021Based in Yokkaichi, JP· patent location history
2016–2018Based in Tokyo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 21 | 2016–2021 |
| SANDISK TECHNOLOGIES INC | 6 | 2016–2017 |
| MATSUSHITA ELECTRIC INDUSTRIAL CO LTD | 4 | 2004–2007 |
| PANASONIC CORP | 2 | 2008–2010 |
| TDK CORP | 2 | 2016–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yokkaichi, JP | 23 | 2016–2021 |
| Kyoto, JP | 4 | 2004–2010 |
| Tokyo, JP | 2 | 2016–2018 |
| Nishikamo-gun, JP | 2 | 2007–2008 |
| Kawasaki, JP | 1 | 2011 |