Inventor
Minghao Shen
Inventor
Sunnyvale, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices24%
H01LSemiconductor devices22%
H10BElectronic memory devices20%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1016%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein4%
H05KPrinted circuits4%
G09GArrangements or circuits for control of indicating devices using static means to present variable information2%
PatentTitleYear
10,734,326Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage202010,424,524Multiple wafers fabrication technique on large carrier with warpage control stiffener201910,347,509Molded cavity fanout package without using a carrier and method of manufacturing the same201910,209,542System and method of embedding driver IC (EmDIC) in LCD display substrate201910,209,597System and method of manufacturing frameless LCD display20199,842,820'Wafer-level fan-out wirebond packages'20179,806,061'Bumpless wafer level fan-out package'20179,425,125'Silicon-glass hybrid interposer circuitry'20169,385,060'Integrated circuit package with enhanced thermal conduction'20169,245,895'Oro and orpro with bit line trench to suppress transport program disturb'20169,224,748'Method of forming spaced-apart charge trapping stacks'20158,039,891'Split charge storage node outer spacer process'20118,012,830'ORO and ORPRO with bit line trench to suppress transport program disturb'20117,883,963'Split charge storage node outer spacer process'20117,867,848'Methods for fabricating dual bit flash memory devices'20117,829,936'Split charge storage node inner spacer process'20107,732,281'Methods for fabricating dual bit flash memory devices'20107,705,390'Dual bit flash memory devices and methods for fabricating the same'20107,687,360'Method of forming spaced-apart charge trapping stacks'20107,635,627'Methods for fabricating a memory device including a dual bit memory cell'20097,368,347'Dual bit flash memory devices and methods for fabricating the same'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2011Patents assigned to SPANSION LLC (10)· patent assignee history
2008–2016Based in Sunnyvale, CA, US· patent location history
2015–2016Patents assigned to CHENG NING (2)· patent assignee history
2015–2016Patents assigned to CYPRESS SEMICONDUCTOR CORP (2)· patent assignee history
2016–2017Patents assigned to ALTERA CORP (4)· patent assignee history
2016–2020Based in San Jose, CA, US· patent location history
2019–2020Patents assigned to DIDREW TECH BVI LIMITED (5)· patent assignee history
2019Based in Santa Clara, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SPANSION LLC | 10 | 2008–2011 |
| DIDREW TECH BVI LIMITED | 5 | 2019–2020 |
| ALTERA CORP | 4 | 2016–2017 |
| CHENG NING | 2 | 2015–2016 |
| CYPRESS SEMICONDUCTOR CORP | 2 | 2015–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 12 | 2008–2016 |
| San Jose, California, US | 7 | 2016–2020 |
| Santa Clara, California, US | 2 | 2019 |