Inventor
Toshio Okochi
Inventor
Musashino, JP
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing43%
H04LTransmission of digital information, e.g. telegraphic communication16%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes8%
E04GScaffolding3%
G06KGraphical data reading3%
G06VImage or video recognition or understanding3%
G16HHealthcare informatics, i.e. information and communication technology [ict] specially adapted for the handling or processing of medical or healthcare data3%
H01LSemiconductor devices3%
H02JElectric power networks3%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems3%
PatentTitleYear
10,552,674Computer, document identification method, and system202010,468,888Control system for solar power plant20198,266,450'Information processing device, encryption method of instruction code, and decryption method of encrypted instruction code'20128,248,241'Assembly work supporting method and system'20128,234,584'Computer system, information collection support device, and method for supporting information collection'20128,094,975'System and method for factory work logging'20128,009,827'Encryption processing method and encryption processing device'20117,693,675'Method for protection of sensor node\'s data, a systems for secure transportation of a sensor node and a sensor node that achieves these'20107,664,939'Method and apparatus for detecting false operation of computer'20107,587,221'Sensor network management system'20097,302,252'Authentication systems, wireless communication terminals, and wireless base stations'20077,206,818'Shared memory multiprocessor system'20076,546,471'Shared memory multiprocessor performing cache coherency'20036,510,496'Shared memory multiprocessor system and method with address translation between partitions and resetting of nodes included in other partitions'20036,438,653'Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system'20026,088,770'Shared memory multiprocessor performing cache coherency'20005,752,030'Program execution control in parallel processor system for parallel execution of plural jobs by selected number of processors'19985,426,612'First-in first-out semiconductor memory device'19955,305,441'Data communication system prioritizing data transfer over microcomputer data interrupt processing'19945,255,238'First-in first-out semiconductor memory device'19935,142,628'Microcomputer system for communication'19924,881,167'Data memory system'1989Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1989–2020Patents assigned to HITACHI LTD (20)· patent assignee history
1989–1995Based in Ohme, JP· patent location history
1998–2003Based in Kokubunji, JP· patent location history
2007–2012Based in Musashino, JP· patent location history
2007Based in Pool Lane, GB· patent location history
2012Patents assigned to OKOCHI TOSHIO (4)· patent assignee history
2012Patents assigned to MATSUMOTO KAZUHIKO (2)· patent assignee history
2012Patents assigned to SUZUKI KEI (2)· patent assignee history
2012Patents assigned to AZUMA AKIO (1)· patent assignee history
2012–2020Based in Tokyo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 20 | 1989–2020 |
| OKOCHI TOSHIOself | 4 | 2012 |
| MATSUMOTO KAZUHIKO | 2 | 2012 |
| SUZUKI KEI | 2 | 2012 |
| AZUMA AKIO | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Musashino, JP | 7 | 2007–2012 |
| Ohme, JP | 5 | 1989–1995 |
| Tokyo, JP | 4 | 2012–2020 |
| Kokubunji, JP | 3 | 1998–2003 |
| Pool Lane, GB | 1 | 2007 |