Inventor
Tomoe Yamamoto
Inventor
Kanagawa, JP
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices21%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
C23CCoating metallic material14%
H10BElectronic memory devices14%
G11CStatic stores7%
G01BMeasuring length, thickness or similar linear dimensions2%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein2%
G05DSystems for controlling or regulating non-electric variables2%
G06FElectric digital data processing2%
G06TImage data processing or generation, in general2%
PatentTitleYear
11,019,322Estimation system and automobile202111,018,420Display device and communication system20218,815,678'Method for fabricating a metal-insulator-metal (MIM) capacitor having capacitor dielectric layer formed by atomic layer deposition (ALD)'20148,304,021'Vapor phase deposition apparatus, method for depositing thin film and method for manufacturing semiconductor device'20128,212,299'Semiconductor device having a thin film capacitor of a MIM (metal-insulator-metal) structure'20128,169,013'Metal-insulator-metal (MIM) capacitor having capacitor dielectric material selected from a group consisting of ZRO2, HFO2, (ZRX, HF1-X)O2 (0<x<1), (ZRy, Ti (O<y<1), (Hfz, Ti-z)O2 (O<z<1) and (Zrk, Ti1, Hfm)O2 (O<K, 1, m<1, K+1+m=1)'20127,943,475'Process for manufacturing a semiconductor device comprising a metal-compound film'20117,608,502'Method for manufacturing semiconductor device'20097,439,181'Method for processing interior of vapor phase deposition apparatus, method for depositing thin film and method for manufacturing semiconductor device'20087,276,444'Method for processing interior of vapor phase deposition apparatus, method for depositing thin film and method for manufacturing semiconductor device'20076,875,667'Method for forming capacitor'20056,596,602'Method of fabricating a high dielectric constant metal oxide capacity insulator film using atomic layer CVD'20036,518,142'Fabrication method for MIM capacitive circuit having little leakage current'20036,399,399'Method for manufacturing semiconductor memory and method for manufacturing capacitor'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2003Patents assigned to NEC CORP (3)· patent assignee history
2002–2014Based in Tokyo, JP· patent location history
2005–2009Patents assigned to NEC ELECTRONICS CORP (4)· patent assignee history
2005–2021Based in Kanagawa, JP· patent location history
2011–2014Patents assigned to RENESAS ELECTRONICS CORP (5)· patent assignee history
2012–2014Patents assigned to YAMAMOTO TOMOE (4)· patent assignee history
2012–2014Patents assigned to IIZUKA TOSHIHIRO (3)· patent assignee history
2012Based in Kawasaki, JP· patent location history
2021Based in Sakai, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RENESAS ELECTRONICS CORP | 5 | 2011–2014 |
| NEC ELECTRONICS CORP | 4 | 2005–2009 |
| YAMAMOTO TOMOEself | 4 | 2012–2014 |
| IIZUKA TOSHIHIRO | 3 | 2012–2014 |
| NEC CORP | 3 | 2002–2003 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kanagawa, JP | 6 | 2005–2021 |
| Tokyo, JP | 6 | 2002–2014 |
| Sakai, JP | 1 | 2021 |
| Kawasaki, JP | 1 | 2012 |