Inventor
Maniam Alagaratnam
Inventor
Cupertino, CA, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1052%
H05KPrinted circuits14%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
Y02PClimate change mitigation technologies in the production or processing of goods7%
Y10TTechnical subjects covered by former us classification7%
B29CShaping or joining of plastics5%
G01RMeasuring electric variables5%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
7,119,432'Method and apparatus for establishing improved thermal communication between a die and a heatspreader in a semiconductor package'20067,041,516'Multi chip module assembly'20066,777,314'Method of forming electrolytic contact pads including layers of copper, nickel, and gold'20046,618,938'Interposer for semiconductor package assembly'20036,608,376'Integrated circuit package substrate with high density routing mechanism'20036,586,825'Dual chip in package with a wire bonded die mounted to a substrate'20036,433,565'Test fixture for flip chip ball grid array circuits'20026,429,534'Interposer tape for semiconductor package'20026,335,491'Interposer for semiconductor package assembly'20026,297,550'Bondable anodized aluminum heatspreader for semiconductor packages'20016,225,695'Grooved semiconductor die for flip-chip heat sink attachment'20016,110,815'Electroplating fixture for high density substrates'20006,081,997'System and method for packaging an integrated circuit using encapsulant injection'20006,057,594'High power dissipating tape ball grid array package'20005,927,505'Overmolded package body on a substrate'19995,923,047'Semiconductor die having sacrificial bond pads for die test'19995,886,398'Molded laminate package with integral mold gate'19995,869,889'Thin power tape ball grid array package'19995,841,191'Ball grid array package employing raised metal contact rings'19985,841,198'Ball grid array package employing solid core solder balls'19985,814,881'Stacked integrated chip package and method of making same'19985,744,084'Method of improving molding of an overmolded package body on a substrate'19985,386,144'Snap on heat sink attachment'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2006Patents assigned to LSI LOGIC CORP (23)· patent assignee history
1995–2006Based in Cupertino, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| LSI LOGIC CORP | 23 | 1995–2006 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 23 | 1995–2006 |