Inventor
John F. Bulzacchelli
Inventor
Yonkers, NY, US
Overview
Patents· 55 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Lprimary
H04LTransmission of digital information, e.g. telegraphic communication22%
H03KPulse technique16%
H04BTransmission11%
H03FAmplifiers8%
G05FSystems for regulating electric or magnetic variables6%
G11CStatic stores5%
H01QAntennas, i.e. radio aerials5%
H03GControl of amplification5%
H03MCoding5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%
PatentTitleYear
10,924,310Transmitter with fully re-assignable segments for reconfigurable FFE taps202110,749,489Dynamic phased array tapering without phase recalibration202010,715,161Analog-to-digital converters with resistor digital-to-analog converters for reference voltage tuning202010,693,429Dynamic phased array tapering without phase recalibration202010,686,643Discrete time analog front end circuit implemented in a receiver device202010,298,190Dynamic phased array tapering without phase recalibration201910,097,383High speed DFEs with direct feedback201810,069,409Distributed voltage regulation system for mitigating the effects of IR-drop201810,033,270Dynamic voltage regulation201810,008,995Dynamic phased array tapering without phase recalibration20189,806,699'Circuits and methods for DFE with reduced area and power consumption'20179,793,913'Single-flux-quantum probabilistic digitizer'20179,614,532'Single-flux-quantum probabilistic digitizer'20179,541,935'Passgate strength calibration techniques for voltage regulators'20179,531,086'Dynamic phased array tapering without phase recalibration'20169,467,313'Continuous-time linear equalizer for high-speed receiving unit'20169,444,437'Circuits and methods for DFE with reduced area and power consumption'20169,369,263'Calibration of sampling phase and aperature errors in multi-phase sampling systems'20169,335,370'On-chip test for integrated AC coupling capacitors'20169,288,085'Continuous-time linear equalizer for high-speed receiving unit'20169,231,796'Power aware equalization in a serial communications link'20169,008,169'Circuits and methods for DFE with reduced area and power consumption'20158,981,829'Passgate strength calibration techniques for voltage regulators'20158,964,826'Time domain analog multiplication techniques for adjusting tap weights of feed-forward equalizers'20158,964,825'Analog signal current integrators with tunable peaking function'20158,941,415'Edge selection techniques for correcting clock duty cycle'20158,913,655'Feed-forward equalizer architectures'20148,841,893'Dual-loop voltage regulator architecture with high DC accuracy and fast response time'20148,779,865'Ultra-compact PLL with wide tuning range and low noise'20148,774,228'Timing recovery method and apparatus for an input/output bus with link redundancy'20148,755,220'Hybrid superconducting-magnetic memory cell and array'20148,755,428'Feed-forward equalizer architectures'20148,704,583'Capacitive level-shifting circuits and methods for adding DC offsets to output of current-integrating amplifier'20148,686,764'Edge selection techniques for correcting clock duty cycle'20148,681,839'Calibration of multiple parallel data communications lines for high skew conditions'20148,633,764'Restoring output common-mode of amplifier via capacitive coupling'20148,624,632'Sense amplifier-type latch circuits with static bias current for enhanced operating frequency'20148,575,905'Dual loop voltage regulator with bias voltage capacitor'20138,564,352'High-resolution phase interpolators'20138,558,611'Peaking amplifier with capacitively-coupled parallel input stages'20138,558,597'High-resolution phase interpolators'20138,547,732'Hybrid superconducting-magnetic memory cell and array'20138,477,833'Circuits and methods for DFE with reduced area and power consumption'20138,294,525'Technique for linearizing the voltage-to-frequency response of a VCO'20128,208,288'Hybrid superconducting-magnetic memory cell and array'20128,183,948'Ultra-compact PLL with wide tuning range and low noise'20128,138,840'Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control'20128,126,045'System and method for latency reduction in speculative decision feedback equalizers'20128,085,841'Sampled current-integrating decision feedback equalizer and method'20117,893,861'Time-to-digital based analog-to-digital converter architecture'20117,822,114'Decision feedback equalizer using soft decisions'20107,792,185'Methods and apparatus for calibrating output voltage levels associated with current-integrating summing amplifier'20107,792,187'Multi-tap decision feedback equalizer (DFE) architecture eliminating critical timing path for higher-speed operation'20107,733,984'Implementing phase rotator circuits with embedded polyphase filter network stage'20107,715,474'Decision feedback equalizer (DFE) architecture'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2021Patents assigned to IBM (52)· patent assignee history
2010–2017Based in Yonkers, NY, US· patent location history
2011–2017Patents assigned to BULZACCHELLI JOHN F (18)· patent assignee history
2011–2014Patents assigned to FRIEDMAN DANIEL J (6)· patent assignee history
2011–2014Patents assigned to RYLYAKOV ALEXANDER V (5)· patent assignee history
2011–2016Based in Yorktown Heights, NY, US· patent location history
2012–2014Patents assigned to RYLOV SERGEY V (5)· patent assignee history
2012Based in Yonker, NY, US· patent location history
2016–2021Based in Somers, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 52 | 2010–2021 |
| BULZACCHELLI JOHN Fself | 18 | 2011–2017 |
| FRIEDMAN DANIEL J | 6 | 2011–2014 |
| RYLOV SERGEY V | 5 | 2012–2014 |
| RYLYAKOV ALEXANDER V | 5 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Yonkers, New York, US | 37 | 2010–2017 |
| Somers, New York, US | 11 | 2016–2021 |
| Yorktown Heights, New York, US | 6 | 2011–2016 |
| Yonker, New York, US | 1 | 2012 |