Inventor
Todd P. Albertson
Inventor
Warren, OR, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G01Rprimary
G01RMeasuring electric variables38%
H05KPrinted circuits13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10TTechnical subjects covered by former us classification10%
G01BMeasuring length, thickness or similar linear dimensions5%
H01LSemiconductor devices5%
H01RElectrically-conductive connections5%
B21GMaking needles, pins or nails of metal3%
B21JForging3%
F25BRefrigeration machines, plants or systems3%
PatentTitleYear
10,939,545Methods and apparatus for flex circuit and cable attachment system202110,598,696Probe pins with etched tips for electrical die test202010,578,647Probes for wafer sorting202010,096,953Methods and apparatus for shielded and grounded cable system20189,977,054Etching for probe wire tips for microelectronic device test20189,823,273'Probe tip formation for die sort and test'20179,581,639'Organic space transformer attachment and assembly'20179,535,095'Anti-rotation for wire probes in a probe head of a die tester'20179,354,273'Composite wire probe test assembly'20169,279,854'Mechanism for facilitating modular processing cell framework and application for asynchronous parallel singulated semiconductor device handling and testing'20169,255,945'Micro positioning test socket and methods for active precision alignment and co-planarity feedback'20169,207,258'Composite wire probes for testing integrated circuits'20159,134,343'Sort probe gripper'20159,069,014'Wire probe assembly and forming process for die testing'20158,962,482'Multi-layer interconnect with isolation layer'20158,891,235'Thermal interface for multi-chip packages'20148,710,858'Micro positioning test socket and methods for active precision alignment and co-planarity feedback'20147,642,651'Multi-layer interconnect with isolation layer'20107,375,033'Multi-layer interconnect with isolation layer'20087,345,495'Temperature and voltage controlled integrated circuit processes'20086,360,544'Anticyclone powered active thermal control unit'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2020Patents assigned to INTEL CORP (16)· patent assignee history
2002–2016Based in Chandler, AZ, US· patent location history
2008–2015Patents assigned to MICRON TECHNOLOGY INC (3)· patent assignee history
2008–2015Based in Boise, ID, US· patent location history
2014–2017Patents assigned to ALBERTSON TODD P (8)· patent assignee history
2014–2017Patents assigned to SHIA DAVID (5)· patent assignee history
2014–2020Based in Warren, OR, US· patent location history
2018–2021Patents assigned to HIGH SPEED INTERCONNECTS LLC (2)· patent assignee history
2018–2021Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 16 | 2002–2020 |
| ALBERTSON TODD Pself | 8 | 2014–2017 |
| SHIA DAVID | 5 | 2014–2017 |
| MICRON TECHNOLOGY INC | 3 | 2008–2015 |
| HIGH SPEED INTERCONNECTS LLC | 2 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Warren, OR, US | 13 | 2014–2020 |
| Chandler, AZ, US | 3 | 2002–2016 |
| Boise, ID, US | 3 | 2008–2015 |
| Portland, OR, US | 2 | 2018–2021 |