Inventor
Shigetsugu Muramatsu
Inventor
Nagano, JP
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1032%
H05KPrinted circuits25%
Y10TTechnical subjects covered by former us classification13%
H01LSemiconductor devices7%
G01RMeasuring electric variables4%
H10HInorganic light-emitting semiconductor devices having potential barriers3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
C02FTreatment of water, waste water, sewage, or sludge1%
D04BKnitting1%
PatentTitleYear
10,895,535Measurement method, and measuring chip and measuring kit used for the same20219,741,647'Wiring substrate, semiconductor device, and method of manufacturing wiring substrate'20179,084,372'Wiring substrate, light emitting device, and manufacturing method of wiring substrate'20159,029,891'Wiring substrate, light emitting device, and manufacturing method of wiring substrate'20159,000,474'Wiring substrate, light emitting device, and manufacturing method of wiring substrate'20158,835,773'Wiring board and method of manufacturing the same'20148,575,495'Wiring substrate, semiconductor device, and method for manufacturing wiring substrate'20138,508,050'Wiring substrate, semiconductor device, and method for manufacturing wiring substrate'20138,222,532'Method for manufacturing a wiring board'20128,115,300'Wiring substrate and manufacturing method thereof, and semiconductor apparatus'20128,037,596'Method for manufacturing a wiring board'20117,438,945'Method of producing multilayer interconnection board'20087,183,196'Multilayer interconnection board and production method thereof'20077,180,182'Semiconductor component'20076,998,291'Cost-reducing and process-simplifying wiring board and manufacturing method thereof'20066,730,859'Substrate for mounting electronic parts thereon and method of manufacturing same'20046,628,527'Mounting structure for electronic parts and manufacturing method thereof'20036,465,886'Semiconductor device having circuit pattern and lands thereon'20026,455,786'Wiring board and manufacturing method thereof and semiconductor device'20026,444,494'Process of packaging a semiconductor device with reinforced film substrate'20026,420,664'Metal foil having bumps, circuit substrate having the metal foil, and semiconductor device having the circuit substrate'20026,404,214'Substrate for inspecting electronic device, method of manufacturing substrate, and method of inspecting electronic device'20026,335,493'Multilayer wiring board'20026,256,207'Chip-sized semiconductor device and process for making same'20016,242,799'Anisotropic stress buffer and semiconductor device using the same'20016,110,755'Method for manufacturing semiconductor device'20006,011,300'Semiconductor integrated circuit device'20005,943,212'Ceramic circuit board and semiconductor device using same'19995,904,488'Semiconductor integrated circuit device'19995,744,224'Board for mounting semiconductor chip'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2017Patents assigned to SHINKO ELECTRIC IND CO (28)· patent assignee history
1998–2017Based in Nagano, JP· patent location history
2012–2017Patents assigned to MURAMATSU SHIGETSUGU (6)· patent assignee history
2012–2014Patents assigned to KUSAMA YASUHIKO (2)· patent assignee history
2013Patents assigned to SUNOHARA SATOSHI (2)· patent assignee history
2017Patents assigned to KATAGIRI NORITAKA (1)· patent assignee history
2021Based in Hino, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SHINKO ELECTRIC IND CO | 28 | 1998–2017 |
| MURAMATSU SHIGETSUGUself | 6 | 2012–2017 |
| KUSAMA YASUHIKO | 2 | 2012–2014 |
| SUNOHARA SATOSHI | 2 | 2013 |
| KATAGIRI NORITAKA | 1 | 2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nagano, JP | 29 | 1998–2017 |
| Hino, JP | 1 | 2021 |