Inventor
Pradeep Vukkadala
Inventor
Fremont, CA, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices16%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
G01BMeasuring length, thickness or similar linear dimensions13%
G06FElectric digital data processing11%
H01LSemiconductor devices10%
G01NInvestigating or analysing materials by determining their chemical or physical properties8%
G06TImage data processing or generation, in general8%
B24BMachines, devices, or processes for grinding or polishing3%
G06KGraphical data reading3%
G06NComputing arrangements based on specific computational models3%
PatentTitleYear
10,788,759Prediction based chucking and lithography control optimization202010,576,603Patterned wafer geometry measurements for semiconductor process controls202010,401,279Process-induced distortion prediction and feedforward and feedback correction of overlay errors201910,379,061Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool201910,249,523Overlay and semiconductor process control using a wafer geometry metric201910,036,964Prediction based chucking and lithography control optimization201810,025,894System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking20189,779,202'Process-induced asymmetry detection, quantification, and control using patterned wafer geometry measurements'20179,707,660'Predictive wafer modeling based focus error prediction using correlations of wafers'20179,558,545'Predicting and controlling critical dimension issues and pattern defectivity in wafers using interferometry'20179,546,862'Systems, methods and metrics for wafer high order shape characterization and wafer classification using wafer dimensional geometry tool'20179,513,565'Using wafer geometry to improve scanner correction effectiveness for overlay control'20169,430,593'System and method to emulate finite element model based prediction of in-plane distortions due to semiconductor wafer chucking'20169,373,165'Enhanced patterned wafer geometry measurements based design improvements for optimal integrated chip fabrication performance'20169,354,526'Overlay and semiconductor process control using a wafer geometry metric'20169,177,370'Systems and methods of advanced site-based nanotopography for wafer surface metrology'20159,052,190'Bright-field differential interference contrast system with scanning beams of round and elliptical cross-sections'20159,029,810'Using wafer geometry to improve scanner correction effectiveness for overlay control'2015Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2015–2020Patents assigned to KLA TENCOR CORP (18)· patent assignee history
2015–2020Based in Fremont, CA, US· patent location history
2016Patents assigned to SINHA JAYDEEP K (1)· patent assignee history
2016Patents assigned to VEERARAGHAVAN SATHISH (1)· patent assignee history
2016Patents assigned to VUKKADALA PRADEEP (1)· patent assignee history
2017–2020Based in Newark, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| KLA TENCOR CORP | 18 | 2015–2020 |
| SINHA JAYDEEP K | 1 | 2016 |
| VEERARAGHAVAN SATHISH | 1 | 2016 |
| VUKKADALA PRADEEPself | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Fremont, California, US | 13 | 2015–2020 |
| Newark, California, US | 5 | 2017–2020 |