LexDanaLexDanabeta
Inventor

Alvin J. Joseph

Inventor
Williston, VT, US

Overview

124→
Patents
2004–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 124 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H01LSemiconductor devices14%
G06FElectric digital data processing4%
H01PWaveguides1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
G01RMeasuring electric variables0%
G02BOptical elements, systems or apparatus0%
H01QAntennas, i.e. radio aerials0%
PatentTitleYear
10,692,753Semiconductor structure with airgap202010,644,654Hybrid cascode constructions with multiple transistor types202010,439,053Cascode heterojunction bipolar transistor201910,367,084Cascode heterojunction bipolar transistors201910,367,083Compact device structures for a bipolar junction transistor201910,340,352Field-effect transistors with a T-shaped gate electrode201910,211,146Air gap over transistor gate and related method201910,211,087Semiconductor structure with airgap201910,157,777Air gap over transistor gate and related method201810,134,880Self-aligned bipolar junction transistors with a base grown in a dielectric cavity201810,062,711Wafers and device structures with body contacts20189,978,849SOI-MOSFET gate insulation layer with different thickness20189,917,005'Semiconductor structure with airgap'20189,847,415Field effect transistor and method of manufacture20179,728,603'Bipolar junction transistors with double-tapered emitter fingers'20179,728,838'On chip antenna with opening'20179,666,475'Semiconductor structure with airgap'20179,633,894'Semiconductor structure with airgap'20179,570,564'Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance'20179,530,711'Silicon-on-insulator heat sink'20169,496,250'Tunable scaling of current gain in bipolar junction transistors'20169,385,022'Silicon waveguide on bulk silicon substrate and methods of forming'20169,349,793'Semiconductor structure with airgap'20169,257,324'Forming structures on resistive substrates'20169,231,087'Bipolar junction transistors with self-aligned terminals'20169,214,561'Thin body switch transistor'20159,171,121'Method, structure, and design structure for a through-silicon-via Wilkinson power divider'20159,165,819'High linearity SOI wafer for low-distortion circuit applications'20159,076,810'Scaling of bipolar transistors'20159,070,651'Non-linear kerf monitor and design structure thereof'20159,059,269'Silicon-on-insulator heat sink'20159,059,196'Bipolar junction transistors with self-aligned terminals'20158,963,293'High resistivity silicon-on-insulator substrate and method of forming'20158,951,896'High linearity SOI wafer for low-distortion circuit applications'20158,921,190'Field effect transistor and method of manufacture'20148,916,467'SOI radio frequency switch with enhanced signal fidelity and electrical isolation'20148,901,676'Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) having a high drain-to-body breakdown voltage (Vb), a method of forming an LEDMOSFET, and a silicon-controlled rectifier (SCR) incorporating a complementary pair of LEDMOSFETs'20148,900,964'Inductors and wiring structures fabricated with limited wiring material'20148,872,236'Scaling of bipolar transistors'20148,866,226'SOI radio frequency switch with enhanced electrical isolation'20148,853,043'Silicon germanium (SiGe) heterojunction bipolar transistor (HBT)'20148,828,746'Compensation for a charge in a silicon substrate'20148,748,308'Through wafer vias and method of making same'20148,741,739'High resistivity silicon-on-insulator substrate and method of forming'20148,735,986'Forming structures on resistive substrates'20148,722,508'Low harmonic RF switch in SOI'20148,716,837'Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases'20148,709,903'Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure'20148,698,244'Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method'20148,692,288'Heterojunction bipolar transistors and methods of manufacture'20148,674,472'Low harmonic RF switch in SOI'20148,652,919'Tunable semiconductor device'20148,633,106'Heterojunction bipolar transistors and methods of manufacture'20148,564,067'Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure'20138,536,012'Bipolar junction transistors with a link region connecting the intrinsic and extrinsic bases'20138,536,035'Silicon-on-insulator substrate and method of forming'20138,518,787'Through wafer vias and method of making same'20138,492,272'Passivated through wafer vias in low-doped semiconductor substrates'20138,492,843'Lateral hyperabrupt junction varactor diode in an SOI substrate'20138,492,868'Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer'20138,482,067'Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates to achieve a high drain-to-body breakdown voltage, a method of forming the transistor and a program storage device for designing the transistor'20138,471,340'Silicon-on-insulator (SOI) structure configured for reduced harmonics and method of forming the structure'20138,436,446'Method, structure, and design structure for a through-silicon-via Wilkinson power divider'20138,415,763'Tunable semiconductor device'20138,405,186'Transistor structure with a sidewall-defined intrinsic base to extrinsic base link-up region and method of forming the structure'20138,384,224'Through wafer vias and method of making same'20138,299,500'Silicon germanium heterojunction bipolar transistor having interstitial trapping layer in base region'20128,299,558'Self-aligned Schottky diode'20128,299,547'Lateral extended drain metal oxide semiconductor field effect transistor (LEDMOSFET) with tapered dielectric plates'20128,299,566'Through wafer vias and method of making same'20128,288,821'SOI (silicon on insulator) substrate improvements'20128,237,191'Heterojunction bipolar transistors and methods of manufacture'20128,234,606'Metal wiring structure for integration with through substrate vias'20128,216,912'Method, structure, and design structure for a through-silicon-via Wilkinson power divider'20128,216,890'Lateral hyperabrupt junction varactor diode in an SOI substrate'20128,163,612'Silicon germanium heterostructure barrier varactor'20128,133,774'SOI radio frequency switch with enhanced electrical isolation'20128,125,007'Integrated circuit including FinFET RF switch angled relative to planar MOSFET and related design structure'20128,089,126'Method and structures for improving substrate loss and linearity in SOI substrates'20128,035,198'Through wafer via and method of making same'20118,022,496'Semiconductor structure and method of manufacture'20118,020,128'Scaling of bipolar transistors'20118,008,142'Self-aligned Schottky diode'20117,999,320'SOI radio frequency switch with enhanced signal fidelity and electrical isolation'20117,989,302'Methods of forming a hyper-abrupt P-N junction and design structures for an integrated circuit'20117,968,975'Metal wiring structure for integration with through substrate vias'20117,932,155'Structure and method for performance improvement in vertical bipolar transistors'20117,932,541'High performance collector-up bipolar transistor'20117,927,963'Integrated circuit structure, design structure, and method having improved isolation and harmonics'20117,898,061'Structure for performance improvement in vertical bipolar transistors'20117,851,923'Low resistance and inductance backside through vias and methods of fabricating same'20107,804,151'Integrated circuit structure, design structure, and method having improved isolation and harmonics'20107,804,119'Device structures with a hyper-abrupt P-N junction, methods of forming a hyper-abrupt P-N junction, and design structures for an integrated circuit'20107,776,704'Method to build self-aligned NPN in advanced BiCMOS technology'20107,772,083'Trench forming method and structure'20107,759,789'Local area semiconductor cooling system'20107,709,338'BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices'20107,701,015'Bipolar and CMOS integration with reduced contact height'20107,696,604'Silicon germanium heterostructure barrier varactor'20107,659,598'Semiconductor ground shield'20107,625,792'Method of base formation in a BiCMOS process'20097,563,714'Low resistance and inductance backside through vias and methods of fabricating same'20097,538,004'Method of fabrication for SiGe heterojunction bipolar transistor (HBT)'20097,521,327'High fT and fmax bipolar transistor and method of making same'20097,501,690'Semiconductor ground shield method'20097,491,985'Method of collector formation in BiCMOS technology'20097,329,940'Semiconductor structure and method of manufacture'20087,317,215'SiGe heterojunction bipolar transistor (HBT)'20087,265,018'Method to build self-aligned NPN in advanced BiCMOS technology'20077,262,484'Structure and method for performance improvement in vertical bipolar transistors'20077,253,096'Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same'20077,119,416'Bipolar transistor structure with self-aligned raised extrinsic base and methods'20067,098,521'Reduced guard ring in schottky barrier diode structure'20067,037,798'Bipolar transistor structure with self-aligned raised extrinsic base and methods'20067,038,298'High fT and fmax bipolar transistor and method of making same'20067,002,221'Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same'20067,002,190'Method of collector formation in BiCMOS technology'20066,967,167'Silicon dioxide removing method'20056,936,910'BiCMOS technology on SOI substrates'20056,911,681'Method of base formation in a BiCMOS process'20056,888,221'BICMOS technology on SIMOX wafers'20056,869,852'Self-aligned raised extrinsic base bipolar transistor structure and method'20056,744,079'Optimized blocking impurity placement for SiGe HBTs'20046,744,112'Multiple chip guard rings for integrated circuit and chip guard ring interconnect'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2020Patents assigned to IBM (109)· patent assignee history
2004–2020Based in Williston, VT, US· patent location history
2011–2013Based in Willliston, VT, US· patent location history
2011–2014Based in Essex Junction, VT, US· patent location history
2012–2015Patents assigned to JOSEPH ALVIN J (31)· patent assignee history
2012–2015Patents assigned to BOTULA ALAN B (16)· patent assignee history
2012–2014Patents assigned to SLINKMAN JAMES A (9)· patent assignee history
2015–2020Patents assigned to GLOBALFOUNDRIES INC (21)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1092004–2020
JOSEPH ALVIN Jself312012–2015
GLOBALFOUNDRIES INC212015–2020
BOTULA ALAN B162012–2015
SLINKMAN JAMES A92012–2014
Locations
LocationPatentsSpan
Williston, VT, US1192004–2020
Willliston, VT, US32011–2013
Essex Junction, VT, US22011–2014