Inventor
Shimin Cui
Inventor
Toronto, CA
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing100%
PatentTitleYear
10,656,925Managing aliasing constraints202010,101,979Managing aliasing constraints201810,095,491Data splitting for recursive data structures20189,727,319'Reducing compilation time using profile-directed feedback'20179,535,673'Reducing compilation time using profile-directed feedback'20179,424,011'Recursive expression simplification'20169,405,516'Recursive expression simplification'20169,311,065'Data splitting for multi-instantiated objects'20169,298,630'Optimizing memory bandwidth consumption using data splitting with software caching'20169,110,684'Data splitting for recursive data structures'20159,104,577'Optimizing memory bandwidth consumption using data splitting with software caching'20158,484,630'Code motion based on live ranges in an optimizing compiler'20138,458,679'May-constant propagation'20138,352,684'Optimal cache replacement scheme using a training operation'20138,332,833'Procedure control descriptor-based code specialization for context sensitive memory disambiguation'20128,161,464'Compiling source code'20128,146,070'Method and apparatus for optimizing software program using inter-procedural strength reduction'20128,015,556'Efficient method of data reshaping for multidimensional dynamic array objects in the presence of multiple object instantiations'20117,856,627'Method of SIMD-ization through data reshaping, padding, and alignment'20107,818,731'Method and system for reducing memory reference overhead associated with treadprivate variables in parallel programs'20107,689,977'Open multi-processing reduction implementation in cell broadband engine (CBE) single source compiler'20107,590,977'Method and system for reducing memory reference overhead associated with threadprivate variables in parallel programs'20097,555,748'Method and apparatus for improving data cache performance using inter-procedural strength reduction of global objects'20097,472,382'Method for optimizing software program using inter-procedural strength reduction'2008Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2008–2020Patents assigned to IBM (23)· patent assignee history
2008–2018Based in Toronto, CA· patent location history
2012–2018Patents assigned to CUI SHIMIN (8)· patent assignee history
2012–2015Patents assigned to GAO YAOQING (5)· patent assignee history
2012–2013Patents assigned to SILVERA RAUL ESTEBAN (5)· patent assignee history
2012–2013Patents assigned to ARCHAMBAULT ROCH GEORGES (4)· patent assignee history
2020Based in Ontario, CA· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 23 | 2008–2020 |
| CUI SHIMINself | 8 | 2012–2018 |
| GAO YAOQING | 5 | 2012–2015 |
| SILVERA RAUL ESTEBAN | 5 | 2012–2013 |
| ARCHAMBAULT ROCH GEORGES | 4 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Toronto, CA | 23 | 2008–2018 |
| Ontario, CA | 1 | 2020 |