Inventor

Samuel D. Naffziger

Inventor

Fort Collins, CO, US

Overview

1997–2021

Patent span

Physics

Primary field (CPC G)

Patents· 141 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing38%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use14%

H03KPulse technique13%

G11CStatic stores9%

G01RMeasuring electric variables9%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%

H04LTransmission of digital information, e.g. telegraphic communication2%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

H03MCoding2%

PatentTitleYear

11,073,888Platform power manager for rack level power and thermal constraints2021 11,054,883Power efficiency optimization in throughput-based workloads2021 10,644,826Flexibile interfaces using through-silicon via technology2020 10,452,554Adaptive resizable cache/LCM for improved power2019 10,431,517Arrangement and thermal management of 3D stacked dies2019 10,303,398Swizzling in 3D stacked memory2019 10,060,955Calibrating power supply voltages using reference measurements from code loop executions2018 9,958,921Power management to change power limits based on device skin temperature2018 9,772,676'Adaptive voltage scaling based on stage transitions or ring oscillator revolutions'2017 9,727,435'Method and system of sampling to automatically scale digital power estimates with frequency'2017 9,710,034'Using temperature margin to balance performance with power allocation'2017 9,671,767'Hybrid system and method for determining performance levels based on thermal conditions within a processor'2017 9,575,553'Replica path timing adjustment and normalization for adaptive voltage and frequency scaling'2017 9,483,092'Performance state boost for multi-core integrated circuit'2016 9,319,037'Self-adjusting clock doubler and integrated circuit clock distribution system using same'2016 9,182,803'Load step mitigation method and apparatus'2015 9,170,631'Adaptive temperature and power calculation for integrated circuits'2015 9,092,219'Method and system of sampling to automatically scale digital power estimates with frequency'2015 9,052,359'Method and system for varying sampling frequency to avoid software harmonics when sampling digital power indicators'2015 9,052,885'Using temperature margin to balance performance with power allocation'2015 8,975,936'Constraining clock skew in a resonant clocked system'2015 8,942,932'Determining transistor leakage for an integrated circuit'2015 8,854,100'Clock driver for frequency-scalable systems'2014 8,836,403'Programmable clock driver'2014 8,793,512'Method and apparatus for thermal control of processing nodes'2014 8,756,442'System for processor power limit management'2014 8,742,817'Controlling impedance of a switch using high impedance voltage sources to provide more efficient clocking'2014 8,710,868'Sense-amplifier monotizer'2014 8,612,781'Method and apparatus for application of power density multipliers optimally in a multicore system'2013 8,595,528'System and method for implementing an integrated circuit having a dynamically variable power limit'2013 8,510,582'Managing current and power in a computing system'2013 8,504,854'Managing multiple operating points for stable virtual frequencies'2013 8,495,395'Mechanism for controlling power consumption in a processing node'2013 8,463,973'Mechanism for voltage regulator load line compensation using multiple voltage settings per operating state'2013 8,456,945'10T SRAM for graphics processing'2013 8,442,786'Flexible power reporting in a computing system'2013 8,276,039'Error detection device and methods thereof'2012 8,266,569'Identification of critical enables using MEA and WAA metrics'2012 8,193,799'Interposer including voltage regulator and method therefor'2012 8,195,962'Method and apparatus for regulating power consumption'2012 8,103,941'Low overhead soft error tolerant flip flop'2012 8,086,884'System and method for implementing an integrated circuit having dynamically variable power limit'2011 8,037,445'System for and method of controlling a VLSI environment'2011 8,010,824'Sampling chip activity for real time power estimation'2011 8,006,115'Central processing unit with multiple clock zones and operating method'2011 7,937,563'Voltage droop mitigation through instruction issue throttling'2011 7,844,838'Inter-die power manager and power management method'2010 7,772,889'Programmable sample clock for empirical setup time selection'2010 7,772,906'Low power flip flop through partially gated slave clock'2010 7,661,003'Systems and methods for maintaining performance of an integrated circuit within a working power limit'2010 7,599,458'System and method to reduce jitter'2009 7,558,317'Edge calibration for synchronous data transfer between clock domains'2009 7,533,285'Synchronizing link delay measurement over serial links'2009 7,512,825'Responding to DC power degradation'2009 7,477,712'Adaptable data path for synchronous data transfer between clock domains'2009 7,447,919'Voltage modulation for increased reliability in an integrated circuit'2008 7,447,941'Error recovery systems and methods for execution data paths'2008 7,401,245'Count calibration for synchronous data transfer between clock domains'2008 7,394,301'System and method for dynamically varying a clock signal'2008 7,323,920'Soft-error rate improvement in a latch using low-pass filtering'2008 7,321,482'Sub-circuit voltage manipulation'2008 7,289,587'Repeatability over communication links'2007 7,276,952'Clock signal generation using digital frequency synthesizer'2007 7,239,494'System and method to mitigate voltage fluctuations'2007 7,224,563'Method and device for circuit control'2007 7,199,611'System to temporarily modify an output waveform'2007 7,157,895'Systems and methods for generating a current'2007 7,148,755'System and method to adjust voltage'2006 7,123,104'System and method for measuring current'2006 7,091,796'Method and system for calibration of a voltage controlled oscillator (VCO)'2006 7,076,679'System and method for synchronizing multiple variable-frequency clock generators'2006 7,068,081'Frequency synthesizer with digital phase selection'2006 7,051,242'Method and apparatus for improving yield by decommissioning optional units on a CPU due to manufacturing defects'2006 7,047,437'Method and system for detecting dropped micro-packets'2006 7,035,134'Memory system and associated methodology'2006 7,028,196'System, method and apparatus for conserving power consumed by a system having a processor integrated circuit'2006 6,954,706'Method for measuring integrated circuit processor power demand and associated system'2005 6,943,586'Method and system to temporarily modify an output waveform'2005 6,931,489'Apparatus and methods for sharing cache among processors'2005 6,927,605'System and method for dynamically varying a clock signal'2005 6,922,783'Method and apparatus for conserving power on a multiprocessor integrated circuit'2005 6,892,294'Identifying execution ready instructions and allocating ports associated with execution resources in an out-of-order processor'2005 6,832,300'Methods and apparatus for control of asynchronous cache'2004 6,820,167'Configurable crossbar and related methods'2004 6,804,793'Manipulating an integrated circuit clock in response to early detection of an operation known to trigger an internal disturbance'2004 6,791,906'Method and system for fail-safe control of a frequency synthesizer'2004 6,789,167'Method and apparatus for multi-core processor integrated circuit having functional elements configurable as core elements and as system device elements'2004 6,772,277'Method of writing to a memory array using clear enable and column clear signals'2004 6,697,929'Scannable zero-catcher and one-catcher circuits for reduced clock loading and power dissipation'2004 6,675,118'System and method of determining the noise sensitivity characterization for an unknown circuit'2004 6,643,828'Method for controlling critical circuits in the design of integrated circuits'2003 6,640,283'Apparatus for cache compression engine for data compression of on-chip caches to increase effective cache size'2003 6,631,506'Method and apparatus for identifying switching race conditions in a circuit design'2003 6,621,310'Reducing power consumption variability of precharge-pulldown busses'2003 6,622,284'Method and apparatus for detection of errors in one-hot words'2003 6,606,720'Scan structure for CMOS storage elements'2003 6,586,971'Adapting VLSI clocking to short term voltage transients'2003 6,583,650'Latching annihilation based logic gate'2003 6,560,737'Method for adding scan controllability and observability to domino CMOS with low area and delay overhead'2003 6,556,501'Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impendance state during write operations'2003 6,549,605'Limiting loss in a circuit'2003 6,539,527'System and method of determining the noise sensitivity of an integrated circuit'2003 6,509,788'System and method utilizing on-chip voltage controlled frequency modulation to manage power consumption'2003 6,493,855'Flexible cache architecture using modular arrays'2002 6,489,834'System and method utilizing on-chip voltage monitoring to manage power consumption'2002 6,483,348'Reducing power consumption variability of static busses'2002 6,466,057'Feedback-induced pseudo-NMOS static (FIPNS) logic gate and method'2002 6,459,304'Latching annihilation based logic gate'2002 6,448,837'Reduced current variability I/O bus termination'2002 6,446,187'Virtual address bypassing using local page mask'2002 6,377,096'Static to dynamic logic interface circuit'2002 6,366,526'Static random access memory (SRAM) array central global decoder system and method'2002 6,363,006'Asymmetric RAM cell'2002 6,359,830'Storage cell on integrated circuit responsive to plural frequency clocks'2002 6,326,829'Pulse latch with explicit, logic-enabled one-shot'2001 6,323,714'System and method for deskewing synchronous clocks in a very large scale integrated circuit'2001 6,313,675'Delay locked loop driver'2001 6,301,186'RAM cell with column clear'2001 6,292,041'Circuit and method for limiting subthreshold leakage'2001 6,281,710'Selective latch for a domino logic gate'2001 6,265,897'Contention based logic gate driving a latch and driven by pulsed clock'2001 6,243,287'Distributed decode system and method for improving static random access memory (SRAM) density'2001 6,240,009'Asymmetric ram cell'2001 6,240,038'Low area impact technique for doubling the write data bandwidth of a memory array'2001 6,188,633'Multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations'2001 6,166,946'System and method for writing to and reading from a memory cell'2000 6,075,386'Dynamic logic gate with relaxed timing requirements and output state holding'2000 6,014,732'Cache memory with reduced access time'2000 5,949,825'Regenerative clamp for multi-drop busses'1999 5,901,061'Method of checking for races in a digital design'1999 5,900,766'Coupling charge compensation device for VLSI circuits'1999 5,892,698'2\'s complement floating-point multiply accumulate unit'1999 5,889,979'Transparent data-triggered pipeline latch'1999 5,838,944'System for storing processor register data after a mispredicted branch'1998 5,815,432'Single-ended read, dual-ended write SCRAM cell'1998 5,760,608'High speed, low clock load register dump circuit'1998 5,760,610'Qualified universal clock buffer circuit for generating high gain, low skew local clock signals'1998 5,757,687'Method and apparatus for bounding alignment shifts to enable at-speed denormalized result generation in an FMAC'1998 5,757,686'Method of decoupling the high order portion of the addend from the multiply result in an FMAC'1998 5,719,803'High speed addition using Ling\'s equations and dynamic CMOS logic'1998 5,677,863'Method of performing operand increment in a booth recoded multiply array'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2003Patents assigned to HEWLETT PACKARD CO (40)· patent assignee history

1997–2021Based in Fort Collins, CO, US· patent location history

2003–2013Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (55)· patent assignee history

2010–2021Patents assigned to ADVANCED MICRO DEVICES INC (39)· patent assignee history

2012–2015Patents assigned to NAFFZIGER SAMUEL D (21)· patent assignee history

2012–2015Patents assigned to SATHE VISVESH S (6)· patent assignee history

2021Based in Ft. Collins, TX, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HEWLETT PACKARD DEVELOPMENT CO	55	2003–2013
HEWLETT PACKARD CO	40	1997–2003
ADVANCED MICRO DEVICES INC	39	2010–2021
NAFFZIGER SAMUEL Dself	21	2012–2015
SATHE VISVESH S	6	2012–2015

Locations

Location	Patents	Span
Fort Collins, CO, US	140	1997–2021
Ft. Collins, Texas, US	1	2021