Inventor
Tobias Gemmeke
Inventor
Stutensee, DE
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing48%
H03KPulse technique22%
G01RMeasuring electric variables11%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
G11CStatic stores4%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
PatentTitleYear
9,477,419'Memory control system for a non-volatile memory and control method'20169,425,795'Circuit and method for detection and compensation of transistor mismatch'20168,860,502'Method and apparatus for monitoring timing of critical paths'20148,756,263'Binary logic unit and method to operate a binary logic unit'20148,452,824'Binary logic unit and method to operate a binary logic unit'20138,370,409'Electronic computing circuit for operand width reduction for a modulo adder followed by saturation concurrent message processing'20138,312,069'Permute unit and method to operate a permute unit'20128,266,411'Instruction set architecture with instruction characteristic bit indicating a result is not of architectural importance'20127,996,738'Semiconductor chip with a plurality of scannable storage elements and a method for scanning storage elements on a semiconductor chip'20117,962,538'Method of operand width reduction to enable usage of narrower saturation adder'20117,913,132'System and method for scanning sequential logic elements'20117,890,901'Method and system for verifying the equivalence of digital circuits'20117,849,428'Formally deriving a minimal clock-gating scheme'20107,795,914'Circuit design methodology to reduce leakage power'20107,735,038'Design structure to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit'20107,639,046'Method to reduce power consumption within a clock gated synchronous circuit and clock gated synchronous circuit'20097,624,363'Method and apparatus for performing equivalence checking on circuit designs having differing clocking and latching schemes'20097,509,511'Reducing register file leakage current within a processor'20097,502,918'Method and system for data dependent performance increment and power reduction'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2014Patents assigned to IBM (16)· patent assignee history
2009–2014Based in Boeblingen, DE· patent location history
2009–2013Based in Santa Clara, CA, US· patent location history
2010–2013Based in Stutensee, DE· patent location history
2012–2013Patents assigned to GEMMEKE TOBIAS (4)· patent assignee history
2012–2013Patents assigned to MAEDING NICOLAS (2)· patent assignee history
2013Patents assigned to PREISS JOCHEN (2)· patent assignee history
2014–2016Patents assigned to STICHTING IMEC NEDERLAND (3)· patent assignee history
2014Based in Leuven, BE· patent location history
2016Based in Straelen, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 16 | 2009–2014 |
| GEMMEKE TOBIASself | 4 | 2012–2013 |
| STICHTING IMEC NEDERLAND | 3 | 2014–2016 |
| MAEDING NICOLAS | 2 | 2012–2013 |
| PREISS JOCHEN | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Stutensee, DE | 7 | 2010–2013 |
| Boeblingen, DE | 6 | 2009–2014 |
| Santa Clara, California, US | 3 | 2009–2013 |
| Straelen, DE | 2 | 2016 |
| Leuven, BE | 1 | 2014 |