Inventor
Akira Masaki
Inventor
Musashino, JP
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique37%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
G11CStatic stores6%
H10DInorganic electric semiconductor devices6%
B03BSeparating solid materials using liquids or using pneumatic tables or jigs3%
B09BDisposal of solid waste not otherwise provided for3%
B29BPreparation or pretreatment of the material to be shaped3%
B65HHandling thin or filamentary material, e.g. sheets, webs, cables3%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein3%
G05FSystems for regulating electric or magnetic variables3%
PatentTitleYear
7,768,314'Integrated circuit with multidimensional switch topology'20107,217,233'Parallel folding apparatus of folding machine'20077,019,804'Liquid crystal cell with twist angle from 180 to 270 degrees and twisted optical compensating element'20065,852,365'Variable logic circuit and semiconductor integrated circuit using the same'19985,610,535'Programmable two-line, two-phase logic array'19975,436,843'Systems and methods for recycling resources and circulating products'19955,214,318'Semiconductor integrated circuit device having a signal transmission line pair interconnected by propagation delay time control resistance'19935,165,010'Information processing system'19925,146,119'Switching circuit and its signal transmission method'19924,942,320'Transistor circuit with improved .alpha. ray resistant properties'19904,893,174'High density integration of semiconductor circuit'19904,868,420'Flip-flop circuit'19894,748,494'Lead arrangement for reducing voltage variation'19884,725,744'Input buffer circuit and logic circuit using the buffer circuit'19884,723,082'Signal transfer circuit for use in laminated multilayer electric circuit'19884,719,369'Output circuit having transistor monitor for matching output impedance to load impedance'19884,710,854'Hybrid multilayer wiring board'19874,697,110'Fluctuation-free input buffer'19874,686,606'Device for cooling integrated circuit chip'19874,644,385'Cooling module for integrated circuit chips'19874,626,889'Stacked differentially driven transmission line on integrated circuit'19864,586,169'Semiconductor memory circuit and large scale integrated circuit using the same'19864,563,601'Level conversion input circuit'19864,558,395'Cooling module for integrated circuit chips'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–1998Patents assigned to HITACHI LTD (21)· patent assignee history
1985–1988Based in Tokyo, JP· patent location history
1986–1987Based in Meguro-ku, JP· patent location history
1987–2010Based in Musashino, JP· patent location history
2006Patents assigned to NIPPON OIL CORP (1)· patent assignee history
2006Based in Yokohama, JP· patent location history
2007Patents assigned to KOMORI PRINTING MACH (1)· patent assignee history
2007Based in Noda, JP· patent location history
2010Patents assigned to UNIV OKAYAMA NAT UNIV CORP (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HITACHI LTD | 21 | 1985–1998 |
| KOMORI PRINTING MACH | 1 | 2007 |
| NIPPON OIL CORP | 1 | 2006 |
| UNIV OKAYAMA NAT UNIV CORP | 1 | 2010 |
Locations
| Location | Patents | Span |
|---|---|---|
| Musashino, JP | 14 | 1987–2010 |
| Tokyo, JP | 6 | 1985–1988 |
| Meguro-ku, JP | 2 | 1986–1987 |
| Noda, JP | 1 | 2007 |
| Yokohama, JP | 1 | 2006 |