Inventor

Georg Tempel

Inventor
Dresden, DE

Overview

51→
Patents
1998–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 51 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices35%
G11CStatic stores18%
H10DInorganic electric semiconductor devices15%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h107%
H10NElectric solid-state devices not otherwise provided for4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
H01LSemiconductor devices3%
H03KPulse technique2%
B82YSpecific uses or applications of nanostructures1%
PatentTitleYear
9,460,810'Method and device for evaluating a chip manufacturing process'20169,419,619'Chip and method for identifying a chip'20169,299,712'Semiconductor device and method of making same'20169,263,154'Method and device for evaluating a chip manufacturing process'20168,940,603'Method of making semiconductor device'20158,691,660'Semiconductor component with trench isolation and corresponding production method'20148,629,034'Nonvolatile memory element and production method thereof and storage memory arrangement'20148,552,524'Semiconductor component with trench insulation and corresponding production method'20138,377,791'Nonvolatile memory element and production method thereof and storage memory arrangement'20138,247,861'Semiconductor device and method of making same'20128,198,681'Semiconductor component with stress-absorbing semiconductor layer'20128,193,059'Bit line structure and method for the production thereof'20128,159,020'Non-volatile two transistor semiconductor memory cell and method for producing the same'20128,154,090'Non-volatile two-transistor semiconductor memory cell and method for producing the same'20127,923,342'Nonvolatile memory element and production method thereof and storage memory arrangement'20117,847,325'Method of making discrete trap memory (DTM) mediated by fullerenes'20107,709,884'Non-volatile two transistor semiconductor memory cell and method for producing the same'20107,709,836'Detector arrangement, method for the detection of electrical charge carriers and use of an ONO field effect transistor for detection of an electrical charge'20107,687,842'Bit line structure and method for the production thereof'20107,642,544'Production method for semiconductor component with stress-carrying semiconductor layer'20107,541,637'Non-volatile semiconductor memory element and corresponding production and operation method'20097,528,038'Non-volatile two-transistor semiconductor memory cell and method for producing the same'20097,442,756'Polymer for sealing porous materials during chip production'20087,399,673'Method of forming a charge-trapping memory device'20087,361,924'Non-volatile memory element and production method thereof and storage memory arrangement'20087,349,251'Integrated memory circuit arrangement'20087,291,881'Bit line structure and method of fabrication'20077,262,456'Bit line structure and production method thereof'20077,190,022'One transistor flash memory cell'20077,176,088'Bitline structure and method for production thereof'20077,138,333'Process for sealing plasma-damaged, porous low-k materials'20067,113,428'Method for operating a memory cell array'20067,060,558'Method for fabricating a field-effect transistor having a floating gate'20067,026,220'Method for production of charge-trapping memory devices'20067,018,898'Non-volatile two transistor semiconductor memory cell and method for producing the same'20066,909,139'One transistor flash memory cell'20056,800,893'Semiconductor circuit configuration and associated fabrication method'20046,787,843'Nonvolatile semiconductor memory cell and associated semiconductor circuit configuration and method for the fabrication of the circuit configuration'20046,628,544'Flash memory cell and method to achieve multiple bits per cell'20036,531,359'Method for fabricating a memory cell array'20036,468,812'Method for producing a semiconductor memory device with a multiplicity of memory cells'20026,232,169'Method for producing a capacitor'20016,083,765'Method for producing semiconductor memory device having a capacitor'20006,025,626'Nonvolatile memory cell'20005,970,338'Method of producing an EEPROM semiconductor structure'19995,943,255'Read only memory'19995,925,905'MOS circuit configuration for switching high voltages on a semiconductor chip'19995,883,832'Electrically erasable and programmable non-volatile storage location'19995,877,983'Method for selective programming of a non-volatile memory'19995,869,860'Ferroelectric memory device and method for producing the device'19995,828,092'Semiconductor memory device and method for its production'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2000Patents assigned to SIEMENS AG (9)· patent assignee history
1998–2012Based in Munich, DE· patent location history
1999–2003Based in Zorneding, DE· patent location history
2001–2016Patents assigned to INFINEON TECHNOLOGIES AG (41)· patent assignee history
2003–2007Based in Sterrebeek, BE· patent location history
2006–2016Based in Dresden, DE· patent location history
2010Based in München, DE· patent location history
2012–2015Patents assigned to TEMPEL GEORG (9)· patent assignee history
2012–2014Patents assigned to SCHULER FRANZ (6)· patent assignee history
2012–2015Patents assigned to ANDERSEN ERNST-OTTO (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INFINEON TECHNOLOGIES AG412001–2016
SIEMENS AG91998–2000
TEMPEL GEORGself92012–2015
SCHULER FRANZ62012–2014
ANDERSEN ERNST-OTTO22012–2015
Locations
LocationPatentsSpan
Dresden, DE312006–2016
Munich, DE101998–2012
Sterrebeek, BE62003–2007
Zorneding, DE31999–2003
München, DE12010