Inventor
Taehee Cho
Inventor
Irvine, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Mprimary
H03MCoding26%
H04NPictorial communication, e.g. television20%
H03FAmplifiers14%
G06FElectric digital data processing9%
G06KGraphical data reading9%
G06VImage or video recognition or understanding9%
G11CStatic stores6%
H01LSemiconductor devices3%
H03GControl of amplification3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
PatentTitleYear
10,089,514Adaptive reference for differential capacitive measurements20189,823,794'Differential readout for sensor array'20179,740,326'Sensor array with split-drive differential sensing'20179,450,596'Ramp and successive approximation register analog to digital conversion methods, systems and apparatus'20169,343,497'Imagers with stacked integrated circuit dies'20169,148,603'Offset injection in an analog-to-digital converter'20158,581,761'Methods and apparatus for performing code correction for hybrid analog-to-digital converters in imaging devices'20137,961,127'Variable gain stage having same input capacitance regardless of the stage gain'20117,898,337'High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital converter and related methods'20117,889,256'Method and apparatus for reducing temporal row-wise noise in imagers'20117,633,423'Method of and apparatus for reducing settling time of a switched capacitor amplifier'20097,612,701'Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry'20097,564,397'High slew rate amplifier, analog-to-digital converter using same, CMOS imager using the analog-to-digital converter and related methods'20097,471,227'Method and apparatus for decreasing layout area in a pipelined analog-to-digital converter'20087,471,228'Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry'20087,408,496'Method, apparatus and system sharing an operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry'20087,148,833'Sharing operational amplifier between two stages of pipelined ADC and/or two channels of signal processing circuitry'20066,999,374'CMOS image sensor having row decoder capable of shutter timing control'20066,920,078'CMOS image sensor having row decoder capable of shutter timing control'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2006Based in Suwon-si, KR· patent location history
2006–2011Patents assigned to MICRON TECHNOLOGY INC (8)· patent assignee history
2006–2009Based in Los Angeles, CA, US· patent location history
2008–2011Based in Irvine, CA, US· patent location history
2009–2013Patents assigned to APTINA IMAGING CORP (3)· patent assignee history
2013–2016Patents assigned to BAHUKHANDI ASHIRWAD (2)· patent assignee history
2013–2016Patents assigned to CHO TAEHEE (2)· patent assignee history
2013–2016Based in Palo Alto, CA, US· patent location history
2017–2018Patents assigned to SYNAPTICS INC (3)· patent assignee history
2017–2018Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 8 | 2006–2011 |
| APTINA IMAGING CORP | 3 | 2009–2013 |
| SYNAPTICS INC | 3 | 2017–2018 |
| BAHUKHANDI ASHIRWAD | 2 | 2013–2016 |
| CHO TAEHEEself | 2 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Irvine, California, US | 8 | 2008–2011 |
| Palo Alto, California, US | 4 | 2013–2016 |
| San Jose, California, US | 3 | 2017–2018 |
| Los Angeles, California, US | 2 | 2006–2009 |
| Suwon-si, KR | 2 | 2005–2006 |