Inventor
Yueh Yale Ma
Inventor
Los Altos Hills, CA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores29%
H10BElectronic memory devices21%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing6%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%
B60KArrangement or mounting of propulsion units or of transmissions in vehicles2%
B60WConjoint control of vehicle sub-units of different type or different function2%
B60YIndexing scheme relating to aspects cross-cutting vehicle technology2%
F16HGearing2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
11,049,998Electroluminescent display panel and display device202110,967,730Method for switching modes of electromechanical transmission system202110,955,749Guiding device and associated system20219,058,289'Soft information generation for memory systems'20158,938,658'Statistical read comparison signal generation for memory systems'20158,793,543'Adaptive read comparison signal generation for memory systems'20146,798,012'Dual-bit double-polysilicon source-side injection flash EEPROM cell'20046,714,454'Method of operation of a dual-bit double-polysilicon source-side injection flash EEPROM cell'20046,699,753'Method of fabricating an array of non-volatile memory cells'20046,493,262'Method for operating nonvolatile memory cells'20026,346,725'Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines'20026,211,548'Metal-gate non-volatile memory cell'20015,986,941'Programming current limiter for source-side injection EEPROM cells'19995,768,186'High density single poly metal-gate non-volatile memory cell'19985,663,907'Switch driver circuit for providing small sector sizes for negative gate erase flash EEPROMS using a standard twin-well CMOS process'19975,414,693'Self-aligned dual-bit split gate (DSG) flash EEPROM cell'19955,364,806'Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell'19945,280,446'Flash eprom memory circuit having source side programming'19945,278,439'Self-aligned dual-bit split gate (DSG) flash EEPROM cell'19944,327,477'Electron beam annealing of metal step coverage'1982Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–1999Patents assigned to BRIGHT MICROELECTRONICS INC (3)· patent assignee history
1994–1995Based in Los Altos, CA, US· patent location history
1997–2004Based in Los Altos Hills, CA, US· patent location history
2002–2004Patents assigned to WINBOND ELECTRONICS CORP (3)· patent assignee history
2014–2015Patents assigned to MA YUEH YALE (3)· patent assignee history
2014–2015Patents assigned to SANDISK ENTPR IP LLC (3)· patent assignee history
2014–2015Patents assigned to TAI YING YU (3)· patent assignee history
2014–2015Based in Palo Alto, CA, US· patent location history
2021Based in Wuhan, CN· patent location history
2021Based in Beijing, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| BRIGHT MICROELECTRONICS INC | 3 | 1994–1999 |
| MA YUEH YALEself | 3 | 2014–2015 |
| SANDISK ENTPR IP LLC | 3 | 2014–2015 |
| TAI YING YU | 3 | 2014–2015 |
| WINBOND ELECTRONICS CORP | 3 | 2002–2004 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos Hills, California, US | 9 | 1997–2004 |
| Los Altos, California, US | 4 | 1994–1995 |
| Palo Alto, California, US | 3 | 2014–2015 |
| Wuhan, CN | 1 | 2021 |
| Beijing, CN | 1 | 2021 |