Inventor

Seyoung Kim

Inventor

White Plains, NY, US

Overview

2012–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices20%

H10NElectric solid-state devices not otherwise provided for11%

G06NComputing arrangements based on specific computational models10%

H10BElectronic memory devices10%

G11CStatic stores9%

H10DInorganic electric semiconductor devices9%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

G06FElectric digital data processing3%

G09FDisplaying3%

H04RLoudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers3%

PatentTitleYear

10,879,390Boosted vertical field-effect transistor2020 10,840,052Planar gate-insulated vacuum channel transistor2020 10,839,900Parasitic voltage drop compensation in large cross-point arrays2020 10,831,860Alignment techniques to match symmetry point as zero-weight point in analog crosspoint arrays2020 10,832,773Architecture for enabling zero value shifting2020 10,833,268Resistive memory crossbar array with a multilayer hardmask2020 10,797,235Multivalent oxide cap for analog switching resistive memory2020 10,777,648Vertical fin-type bipolar junction transistor with self-aligned base contact2020 10,771,730Display apparatus2020 10,771,899Display apparatus2020 10,763,431Film stress control for memory device stack2020 10,747,213Scheduling optimization system and method in hot press forging process2020 10,748,962Method and structure for forming MRAM device2020 10,748,064Deep neural network training with native devices2020 10,727,407Resistive switching memory with replacement metal electrode2020 10,726,895Circuit methodology for differential weight reading in resistive processing unit devices2020 10,693,059MTJ stack etch using IBE to achieve vertical profile2020 10,672,872Self-aligned base contacts for vertical fin-type bipolar junction transistors2020 10,672,643Reducing off-state leakage current in Si/SiGe dual channel CMOS2020 10,659,858Display apparatus2020 10,651,379Three-terminal metastable symmetric zero-volt battery memristive device2020 10,600,606Vertical vacuum channel transistor with minimized air gap between tip and gate2020 10,599,744Scalable architecture for analog matrix operations with resistive devices2020 10,593,771Vertical fin-type bipolar junction transistor with self-aligned base contact2020 10,567,880Display apparatus2020 10,547,948Display apparatus2020 10,541,329Boosted vertical field-effect transistor2020 10,541,135Source and drain formation using self-aligned processes2020 10,497,752Resistive random-access memory array with reduced switching resistance variability2019 10,468,498Vertical fin bipolar junction transistor with high germanium content silicon germanium base2019 10,468,098In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture2019 10,453,527In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture2019 10,453,844Techniques for enhancing vertical gate-all-around FET performance2019 10,396,126Resistive memory device with electrical gate control2019 10,387,778Scalable architecture for implementing maximization algorithms with resistive devices2019 10,381,429Display device2019 10,381,074Differential weight reading of an analog memory element in crosspoint array utilizing current subtraction transistors2019 10,380,485Scalable architecture for implementing maximization algorithms with resistive devices2019 10,373,051Resistive processing unit2019 10,366,323Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes2019 10,347,456Vertical vacuum channel transistor with minimized air gap between tip and gate2019 10,338,730Display device and timing controller2019 10,340,002In-cell differential read-out circuitry for reading signed weight values in resistive processing unit architecture2019 10,340,447Three-terminal metastable symmetric zero-volt battery memristive device2019 10,325,006Scalable architecture for analog matrix operations with resistive devices2019 10,269,425Circuit methodology for highly linear and symmetric resistive processing unit2019 10,248,907Resistive processing unit2019 10,229,736Memristive device based on reversible intercalated ion transfer between two meta-stable phases2019 10,186,657Three-terminal metastable symmetric zero-volt battery memristive device2019 10,153,159Source and drain formation using self-aligned processes2018 10,141,509Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes2018 10,115,800Vertical fin bipolar junction transistor with high germanium content silicon germanium base2018 10,096,773Crossbar resistive memory array with highly conductive copper/copper alloy electrodes and silver/silver alloys electrodes2018 10,079,341Three-terminal non-volatile multi-state memory for cognitive computing applications2018 9,997,704Scaled cross bar array with undercut electrode2018 9,887,351'Multivalent oxide cap for analog switching resistive memory'2018 9,852,790Circuit methodology for highly linear and symmetric resistive processing unit2017 9,601,546'Scaled cross bar array with undercut electrode'2017 D0769917'Display screen or portion thereof with graphical user interface'2016 D0768717'Display screen or portion thereof with icon'2016 D0768166'Display screen or portion thereof with graphical user interface'2016 D0763918'Display screen or portion thereof with icon'2016 9,203,022'Resistive random access memory devices with extremely reactive contacts'2015 9,054,385'Passive power management and battery charging for a hybrid fuel cell / battery system'2015 8,198,707'Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene'2012

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2012–2015Patents assigned to KIM SEYOUNG (2)· patent assignee history

2015–2020Patents assigned to IBM (51)· patent assignee history

2015–2020Based in White Plains, NY, US· patent location history

2016Patents assigned to SAMSUNG ELECTRONICS CO LTD (4)· patent assignee history

2016Based in Yongin-si, KR· patent location history

2018–2020Based in Mount Kisco, NY, US· patent location history

2019–2020Patents assigned to LG DISPLAY CO LTD (7)· patent assignee history

2019Patents assigned to INT BUSINESS MACHINES INT (2)· patent assignee history

2020Based in Weschester, NY, US· patent location history

2020Based in Seoul, KR· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	51	2015–2020
LG DISPLAY CO LTD	7	2019–2020
SAMSUNG ELECTRONICS CO LTD	4	2016
INT BUSINESS MACHINES INT	2	2019
KIM SEYOUNGself	2	2012–2015

Locations

Location	Patents	Span
White Plains, New York, US	38	2015–2020
Weschester, New York, US	6	2020
Mount Kisco, New York, US	4	2018–2020
Yongin-si, KR	4	2016
Seoul, KR	3	2020