Inventor
JUNG-HUNG CHANG
Inventor
TW
Overview
Patents· 62 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
B82YSpecific uses or applications of nanostructures24%
H01LSemiconductor devices24%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10BElectronic memory devices0%
PatentTitleYear
12,543,352Integrated circuit with bottom dielectric insulators and fin sidewall spacers for reducing source/drain leakage currents202612,538,570Reduction of gate-drain capacitance202612,532,492Structure and formation method of semiconductor device with epitaxial structures202612,520,543Semiconductor device structure and method for forming the same202612,513,937Semiconductor devices and methods of fabrication thereof202512,507,445—202512,484,246Method of manufacturing a semiconductor device including forming a sidewall spacer on a sidewall of a channel structure202512,457,798Dielectric liner for field effect transistors202512,446,305Uniform gate width for nanostructure devices202512,446,275Semiconductor device and manufacturing method thereof202512,446,319Semiconductor device structure and methods of forming the same202512,439,638FET with wrap-around silicide and fabrication methods thereof202512,382,666Enlargement of GAA nanostructure202512,369,384Semiconductor device structure including dielectric region with plurality of different oxidation regions202512,347,775Semiconductor devices with backside power rail and methods of fabrication thereof202512,349,379Semiconductor devices and methods of manufacture202512,342,587Integrated circuit with nanostructure transistors and bottom dielectric insulators202512,342,616Semiconductor device structure and methods of forming the same202512,336,240Transistor including dielectric barrier and manufacturing method thereof202512,336,226Semiconductor device structure including stacked nanostructures202512,317,540Method for manufacturing semiconductor structure with isolation feature202512,300,732Gate all around transistor with dual inner spacers202512,272,732Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof202512,243,780Semiconductor device structure and method for forming the same202512,205,998Semiconductor device with wrap around silicide and hybrid fin202512,107,169Contact structure for stacked multi-gate device202412,074,204Semiconductor structure and method for forming the same202412,051,736Field effect transistor with inner spacer liner layer and method202412,009,216Methods of forming silicide contact in field-effect transistors202412,009,215Semiconductor device structure with silicide layer202411,996,482Semiconductor device202411,996,483FET with wrap-around silicide and fabrication methods thereof202411,984,361Multi-gate devices and method of fabricating the same202411,978,674Semiconductor device structure and methods of forming the same202411,967,594Semiconductor device structure and methods of forming the same202411,929,287Dielectric liner for field effect transistors202411,916,122Gate all around transistor with dual inner spacers202411,901,364Semiconductor device structure and methods of forming the same202411,855,216Inner spacers for gate-all-around transistors202311,855,096Uniform gate width for nanostructure devices202311,764,065Methods of forming silicide contact in field-effect transistors202311,710,774Method for forming epitaxial source/drain features and semiconductor devices fabricated thereof202311,699,760Contact structure for stacked multi-gate device202311,695,076FET with wrap-around silicide and fabrication methods thereof202311,664,230Semiconductor device structure with silicide202311,605,737Semiconductor device and manufacturing method thereof202311,600,529Multi-gate devices and method of fabricating the same202311,581,403Semiconductor device and manufacturing method thereof202311,532,626Reduction of gate-drain capacitance202211,502,034Semiconductor devices with backside power rail and methods of fabrication thereof202211,469,326Semiconductor devices and methods of fabrication thereof202211,450,754Semiconductor devices and methods of manufacture202211,450,663Semiconductor device structure and methods of forming the same202211,430,892Inner spacers for gate-all-around transistors202211,417,777Enlargement of GAA nanostructure202211,398,550Semiconductor device with facet S/D feature and methods of forming the same202211,322,409Multi-gate devices and method of fabricating the same202211,315,925Uniform gate width for nanostructure devices202211,309,187Methods of forming silicide contact in field-effect transistors202211,309,424Semiconductor device and manufacturing method thereof202211,264,502Semiconductor device and method202211,205,711Selective inner spacer implementations2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (62)· patent assignee history
2021–2026Based in TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 62 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 62 | 2021–2026 |