Inventor
Atsuya Okazaki
Inventor
Kawasaki, JP
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing17%
G06NComputing arrangements based on specific computational models17%
G11CStatic stores17%
H04BTransmission8%
H04LTransmission of digital information, e.g. telegraphic communication8%
H04JMultiplex communication6%
H04QSelecting6%
H01LSemiconductor devices4%
H04WWireless communication networks4%
H10BElectronic memory devices4%
PatentTitleYear
10,740,673Scalable refresh for asymmetric non-volatile memory-based neuromorphic circuits202010,672,471Linearly weight updatable CMOS synaptic array without cell location dependence202010,573,387Memory data randomizer202010,559,358Memory data randomizer202010,490,273Linearly weight updatable CMOS synaptic array without cell location dependence201910,445,640Scalable refresh for asymmetric non-volatile memory-based neuromorphic circuits201910,339,444Monitoring potential of neuron circuits201910,319,444Memory data randomizer201910,289,950Monitoring potential of neuron circuits201910,241,917Identification of a computing device accessing a shared memory201910,169,237Identification of a computing device accessing a shared memory201910,095,541Executing memory access while performing task switching20189,940,237Identification of a computing device accessing a shared memory20189,928,175'Identification of a computing device accessing a shared memory'20189,910,789'Electrical and optical memory access'20189,066,289'Packet communication system, communication method and program'20158,913,458'Integrity check of measured signal trace data'20148,902,694'Integrity check of measured signal trace data'20148,644,667'Backplane structure allowing setting of equal peer-to-peer communication distance between two blades arbitrarily inserted into a plurality of fixedly arranged slots'20148,600,233'Arbitration of optical communication bus'20138,442,028'Packet communication system, communication method and program'20138,346,080'Optical network system and memory access method'20138,233,622'Transmitting parallel data via high-speed serial interconnection'20127,577,852'Microprocessor, a node terminal, a computer system and a program execution proving method'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009Based in Ikoma, JP· patent location history
2012–2020Patents assigned to IBM (23)· patent assignee history
2012–2014Patents assigned to OKAZAKI ATSUYA (5)· patent assignee history
2012–2014Patents assigned to KATAYAMA YASUNAO (4)· patent assignee history
2012–2015Based in Kanagawa, JP· patent location history
2014Patents assigned to LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD (1)· patent assignee history
2014–2019Based in Kawasaki, JP· patent location history
2018Patents assigned to IBM JAPAN (1)· patent assignee history
2018–2020Based in Tokyo, JP· patent location history
2019–2020Based in Setagaya, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 23 | 2012–2020 |
| OKAZAKI ATSUYAself | 5 | 2012–2014 |
| KATAYAMA YASUNAO | 4 | 2012–2014 |
| IBM JAPAN | 1 | 2018 |
| LENOVO ENTPR SOLUTIONS SINGAPORE PTE LTD | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kawasaki, JP | 7 | 2014–2019 |
| Kanagawa, JP | 6 | 2012–2015 |
| Tokyo, JP | 5 | 2018–2020 |
| Setagaya, JP | 5 | 2019–2020 |
| Ikoma, JP | 1 | 2009 |