Inventor
Kevin W. McCullen
Inventor
Essex Junction, VT, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing74%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices16%
Y02PClimate change mitigation technologies in the production or processing of goods6%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
PatentTitleYear
9,158,885'Reducing color conflicts in triple patterning lithography'20158,627,247'Systems and methods for fixing pin mismatch in layout migration'20148,538,825'Purchase information notification system, method, and program product'20138,464,189'Technology migration for integrated circuits with radical design restrictions'20138,095,897'Methods and systems for layout and routing using alternating aperture phase shift masks'20127,895,562'Adaptive weighting method for layout optimization with multiple priorities'20117,882,463'Integrated circuit selective scaling'20117,761,821'Technology migration for integrated circuits with radical design restrictions'20107,752,589'Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design'20107,735,042'Context aware sub-circuit layout modification'20107,610,565'Technology migration for integrated circuits with radical design restrictions'20097,568,173'Independent migration of hierarchical designs with methods of finding and fixing opens during migration'20097,543,252'Migration of integrated circuit layout for alternating phase shift masks'20097,484,197'Minimum layout perturbation-based artwork legalization with grid constraints for hierarchical designs'20097,475,379'Methods and systems for layout and routing using alternating aperture phase shift masks'20097,363,601'Integrated circuit selective scaling'20087,302,651'Technology migration for integrated circuits with radical design restrictions'20077,257,783'Technology migration for integrated circuits with radical design restrictions'20077,124,387'Integrated circuit macro placing system and method'20067,120,887'Cloned and original circuit shape merging'20067,117,456'Circuit area minimization using scaling'20066,986,109'Practical method for hierarchical-preserving layout optimization of integrated circuit layout'20066,698,008'Row-based placement scoring and legalization measure for books with phase shift mask dependencies'20045,761,719'On-chip memory map for processor cache macro'1998Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1998–2015Patents assigned to IBM (24)· patent assignee history
1998Based in Jericho, VT, US· patent location history
2004–2015Based in Essex Junction, VT, US· patent location history
2012–2014Patents assigned to MCCULLEN KEVIN W (4)· patent assignee history
2013–2014Patents assigned to NARAYAN RANI (2)· patent assignee history
2013–2014Patents assigned to YUAN XIN (2)· patent assignee history
2013Patents assigned to ALLEN ROBERT J (1)· patent assignee history
2014Based in EssexJunction, VT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 24 | 1998–2015 |
| MCCULLEN KEVIN Wself | 4 | 2012–2014 |
| NARAYAN RANI | 2 | 2013–2014 |
| YUAN XIN | 2 | 2013–2014 |
| ALLEN ROBERT J | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 22 | 2004–2015 |
| EssexJunction, VT, US | 1 | 2014 |
| Jericho, VT, US | 1 | 1998 |