Inventor
TIN-HAO KUO
Inventor
TW
Overview
Patents· 95 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1033%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%
H10DInorganic electric semiconductor devices3%
H05KPrinted circuits2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
Y10TTechnical subjects covered by former us classification1%
B23KSoldering or unsoldering1%
G02BOptical elements, systems or apparatus1%
H01RElectrically-conductive connections1%
PatentTitleYear
12,557,681Semiconductor package and method of manufacturing the same202612,412,817Integrated circuit package and method202512,368,141IPD modules with flexible connection scheme in packaging202512,354,926Package and method for manufacturing the same202512,322,706Chip package and method of forming the same202512,300,571Integrated circuit package and method202512,300,618Semiconductor device having a heat dissipation structure connected chip package202512,278,208Method of fabricating semiconductor structure including a barrier structure in between a plurality of surface mount components and a wafer202512,261,126Semiconductor package202512,255,184Semiconductor packages and methods of forming the same202512,255,196Semiconductor package with thermal relaxation block and manufacturing method thereof202512,255,174Bonding passive devices on active dies to form 3D packages202512,230,513Cross-wafer RDLs in constructed wafers202512,218,006System, device and methods of manufacture202512,205,923Semiconductor device, circuit board structure and manufacturing method thereof202512,199,051Integrated circuit structure and method202512,159,851Package structure having hollow cylinders and method of fabricating the same202412,159,839Semiconductor packages202412,142,597Integrated fan-out package and the methods of manufacturing202412,136,612Three-dimension large system integration202412,125,804Semiconductor package and manufacturing method thereof202412,087,718Bump structure having a side recess and semiconductor structure including the same202412,080,615Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors202412,074,143Integrated circuit package and method202412,057,405Packages with thick RDLs and thin RDLs stacked alternatingly202412,051,666Package structure and manufacturing method of package structure thereof202412,040,281Semiconductor package structure comprising rigid-flexible substrate and manufacturing method thereof202412,014,979Methods of forming semiconductor packages202412,014,976Chip package structure including a silicon substrate interposer and methods for forming the same202412,009,281Package structure and method of manufacturing the same202411,990,381Integrated circuit packages having support rings202411,961,810Solderless interconnection structure and method of forming same202411,923,349Semiconductor structures202411,923,318Method of manufacturing semiconductor package202411,908,706Cross-wafer RDLs in constructed wafers202411,855,016Semiconductor device and method of manufacture202311,854,986Chamfered die of semiconductor package and method for forming the same202311,848,233Semiconductor package and manufacturing method thereof202311,848,235System, device and methods of manufacture202311,848,300Semiconductor structure including a semiconductor wafer and a surface mount component overhanging a periphery of the semiconductor wafer202311,848,319Multi-chip semiconductor package202311,837,575Bonding passive devices on active device dies to form 3D packages202311,830,866Semiconductor package with thermal relaxation block and manufacturing method thereof202311,824,017Semiconductor package and manufacturing method thereof202311,804,443Segregated power and ground design for yield improvement202311,798,925IPD modules with flexible connection scheme in packaging202311,776,905Package structure, package-on-package structure and manufacturing method thereof202311,776,880Surface treatment method and apparatus for semiconductor packaging202311,764,171Integrated circuit structure and method202311,749,640Semiconductor package and method of manufacturing the same202311,749,582Package structure202311,694,966Chip package and method of forming the same202311,694,943Semiconductor device including heat dissipation structure and fabricating method of the same202311,682,626Chamfered die of semiconductor package and method for forming the same202311,682,655Semiconductor packages and methods of forming the same202311,658,143Bump-on-trace design for enlarge bump-to-trace distance202311,646,255Chip package structure including a silicon substrate interposer and methods for forming the same202311,631,648Bump structure having a side recess and semiconductor structure including the same202311,569,202Semiconductor device, circuit board structure and manufacturing method thereof202311,538,788Integrated fan-out stacked package with fan-out redistribution layer (RDL)202211,538,735Method of forming integrated circuit packages with mechanical braces202211,532,529Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors202211,532,594Integrated fan-out package and the methods of manufacturing202211,515,268Semiconductor package and manufacturing method thereof202211,508,656Semiconductor package and method202211,508,671Semiconductor package and manufacturing method thereof202211,508,665Packages with thick RDLs and thin RDLs stacked alternatingly202211,502,013Integrated circuit package and method202211,502,039Semiconductor package and method202211,495,590Multi-chip semiconductor package202211,488,897Integrated circuit package and method202211,456,249Package structure, package-on-package structure and manufacturing method thereof202211,444,002Package structure202211,424,213Semiconductor structure including a first surface mount component and a second surface mount component and method of fabricating the semiconductor structure202211,417,638Semiconductor structures202211,417,633Integrated circuit package and method202211,404,316System, device and methods of manufacture202211,355,466Package structure and manufacturing method of package structure thereof202211,342,295Electronic assembly, package structure having hollow cylinders and method of fabricating the same202211,322,421Package structure and method of forming the same202211,315,805Cross-wafer RDLs in constructed wafers202211,315,896Conical-shaped or tier-shaped pillar connections202211,309,302Manufacturing method of semiconductor package including thermal conductive block202211,309,294Integrated fan-out packages and methods of forming the same202211,296,062Three-dimension large system integration202211,289,373Semiconductor package and manufacturing method thereof202211,282,791Semiconductor device having a heat dissipation structure connected chip package202211,239,135Package structure and method of manufacturing the same202211,211,346Semiconductor device and method of manufacture202111,205,636Semiconductor package and method of manufacturing the same202111,201,118Chip package and method of forming the same202111,183,487Integrated circuit package and method202111,177,192Semiconductor device including heat dissipation structure and fabricating method of the same202111,164,819Semiconductor package and manufacturing method thereof202111,158,576Package structure having redistribution layer structures2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (95)· patent assignee history
2021–2026Based in TW· patent location history
2025Patents assigned to TAIWNA SEMICONDUCTOR MFG COMPANY LTD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 95 | 2021–2026 |
| TAIWNA SEMICONDUCTOR MFG COMPANY LTD | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 95 | 2021–2026 |