Inventor
Deepak Kamalanathan
Inventor
Santa Clara, CA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores47%
H01LSemiconductor devices18%
H10BElectronic memory devices18%
H10NElectric solid-state devices not otherwise provided for18%
PatentTitleYear
11,127,458Non-uniform state spacing in multi-state memory element for low-power operation202111,017,856Soft reset for multi-level programming of memory cells in non-Von Neumann architectures202110,283,567Methods and apparatus for three-dimensional nonvolatile memory201910,283,708Methods and apparatus for three-dimensional nonvolatile memory201910,153,430Germanium-based barrier modulated cell20189,734,902'Resistive memory device with ramp-up/ramp-down program/erase pulse'20179,613,693'Methods for setting a resistance of programmable resistance memory cells and devices including the same'20179,530,495'Resistive switching memory having a resistor, diode, and switch memory cell'20169,524,777'Dual program state cycling algorithms for resistive switching memory device'20169,472,272'Resistive switching memory with cell access by analog signal controlled transmission gate'20169,373,786'Two terminal resistive access devices and methods of formation thereof'20169,368,198'Circuits and methods for placing programmable impedance memory elements in high impedance states'20169,165,644'Method of operating a resistive memory device with a ramp-up/ramp-down program/erase pulse'20159,029,829'Resistive switching memories'20159,025,396'Pre-conditioning circuits and methods for programmable impedance elements in memory devices'20159,007,808'Safeguarding data through an SMT process'20159,001,553'Resistive devices and methods of operation thereof'20158,995,167'Reverse program and erase cycling algorithms'20158,730,752'Circuits and methods for placing programmable impedance memory elements in high impedance states'2014Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2014–2016Patents assigned to ADESTO TECHNOLOGIES CORP (9)· patent assignee history
2014–2016Patents assigned to ECHEVERRY JUAN PABLO SAENZ (4)· patent assignee history
2014–2016Patents assigned to KAMALANATHAN DEEPAK (4)· patent assignee history
2014–2017Based in Santa Clara, CA, US· patent location history
2016–2017Patents assigned to ADESTO TECH CORP (5)· patent assignee history
2018–2019Patents assigned to SANDISK TECHNOLOGIES LLC (3)· patent assignee history
2018–2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADESTO TECHNOLOGIES CORP | 9 | 2014–2016 |
| ADESTO TECH CORP | 5 | 2016–2017 |
| ECHEVERRY JUAN PABLO SAENZ | 4 | 2014–2016 |
| KAMALANATHAN DEEPAKself | 4 | 2014–2016 |
| SANDISK TECHNOLOGIES LLC | 3 | 2018–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 14 | 2014–2017 |
| San Jose, California, US | 5 | 2018–2021 |