Inventor
KEN OOWADA
Inventor
JP
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores38%
H01LSemiconductor devices19%
H10BElectronic memory devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10DInorganic electric semiconductor devices7%
G06FElectric digital data processing5%
PatentTitleYear
12,046,302Edge word line concurrent programming with verify for memory apparatus with on-pitch semi-circle drain side select gate technology202411,901,007Positive TCO voltage to dummy select transistors in 3D memory202411,894,081EP cycling dependent asymmetric/symmetric VPASS conversion in non-volatile memory structures202411,688,469Non-volatile memory with sub-block based self-boosting scheme202311,646,081Reliability compensation for uneven NAND block degradation202311,625,172Programming memory cells with concurrent redundant storage of data for power loss protection202311,551,781Programming memory cells with concurrent storage of multi-level data as single-level data for power loss protection202311,545,221Concurrent programming of multiple cells for non-volatile memory devices202311,501,821Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same202211,397,635Block quality classification at testing for non-volatile memory, and multiple bad block flags for product diversity202211,348,649Threshold voltage setting with boosting read scheme202211,342,006Buried source line structure for boosting read scheme202211,342,029Non-volatile memory with switchable erase methods202211,342,028Concurrent programming of multiple cells for non-volatile memory devices202211,322,483Three-dimensional memory device containing a shared word line driver across different tiers and methods for making the same202211,227,663Boosting read scheme with back-gate bias202211,189,335Double write/read throughput by CMOS adjacent array (CaA) NAND memory2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2024Patents assigned to SANDISK TECHNOLOGIES LLC (17)· patent assignee history
2021–2024Based in JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SANDISK TECHNOLOGIES LLC | 17 | 2021–2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| JP | 17 | 2021–2024 |