Inventor
Yu-Lien Huang
Inventor
Jhubei City, TW
Overview
Patents· 113 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices32%
H01LSemiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%
H10BElectronic memory devices1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
H01JElectric discharge tubes or discharge lamps1%
B82YSpecific uses or applications of nanostructures1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests0%
PatentTitleYear
10,867,842Method for shrinking openings in forming integrated circuits202010,854,749Source/drain structure having multi-facet surfaces202010,840,126FinFET structure with different fin heights and method for forming the same202010,797,058Conductive feature formation202010,784,106Selective film growth for bottom-up gap filling202010,727,347Semiconductor device and a method for fabricating the same202010,714,597FinFETs with low source/drain contact resistance202010,714,578Methods for forming recesses in source/drain regions and devices formed thereof202010,699,943Method of forming contacts in a semiconductor device202010,693,009Structure of S/D contact and method of making same202010,692,720Methods for controlling an end-to-end distance in semiconductor device202010,510,883Asymmetric source and drain structures in semiconductor devices201910,504,770FinFET structure with different fin heights and method for forming the same201910,504,724Selective film growth for bottom-up gap filling201910,504,729Methods for controlling an end-to-end distance in semiconductor device201910,418,456Method of fabricating a semiconductor device having modified profile metal gate201910,367,094Source/drain structure having multi-facet surfaces201910,354,998Structures and methods for fabricating semiconductor devices using fin structures201910,312,089Methods for controlling an end-to-end distance in semiconductor device201910,312,145Asymmetric source/drain epitaxy201910,199,502Structure of S/D contact and method of making same201910,170,332FinFET thermal protection methods and related structures201910,170,305Selective film growth for bottom-up gap filling201910,164,106Semiconductor device and a method for fabricating the same201810,164,067Method of fabricating a semiconductor device201810,164,064FinFETs with low source/drain contact resistance201810,164,116FETs and methods for forming the same201810,158,020Method of forming a semiconductor device with multiple etch stop layers and inter-layer dielectrics201810,134,897Semiconductor device and fabrication method thereof201810,134,638FETS and methods of forming FETS201810,056,407Semiconductor device and a method for fabricating the same201810,050,149Gate structure for semiconductor device201810,032,887Method of forming a contact201810,002,765FinFET structure with different fin heights and method for forming the same20189,997,397Semiconductor structure and manufacturing method thereof20189,991,165Asymmetric source/drain epitaxy20189,953,878Method of forming a semiconductor device20189,911,830'FinFETs with contact-all-around'20189,887,274'FinFETs and methods for forming the same'20189,881,840'Method of fabricating gate electrode using a treated hard mask'20189,876,098Method of forming a gate spacer20189,876,112Source/drain structure and manufacturing the same20189,871,037'Structures and methods for fabricating semiconductor devices using fin structures'20189,859,431'Method of forming a semiconductor device with multiple etch stop layers and inter-layer dielectrics'20189,818,878'FETs and methods for forming the same'20179,812,366'Method of tuning work function for a semiconductor device'20179,780,216'Combination FinFET and methods of forming same'20179,673,292'Semiconductor device having modified profile metal gate'20179,659,932'Semiconductor device having a plurality of fins and method for fabricating the same'20179,653,461'FinFETs with low source/drain contact resistance'20179,627,258'Method of forming a contact'20179,627,539'Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost'20179,620,386'Methods of annealing after deposition of gate layers'20179,620,633'Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure'20179,620,607'Gate all around device structure and Fin field effect transistor (FinFET) device structure'20179,583,598'FETs and methods of forming FETs'20179,564,353'FinFETs with reduced parasitic capacitance and methods of forming the same'20179,559,206'FinFETs with necking in the fins'20179,543,301'Fin-last FinFET and methods of forming same'20179,536,772'Fin structure of semiconductor device'20179,536,738'Vertical gate all around (VGAA) devices and methods of manufacturing the same'20179,496,395'Semiconductor device having a strain feature in a gate spacer and methods of manufacture thereof'20169,450,097'Methods for doping Fin field-effect transistors and Fin field-effect transistor'20169,437,699'Method of forming nanowires'20169,419,141'Replacement channel'20169,412,814'Structure and formation method of FinFET device'20169,406,804'FinFETs with contact-all-around'20169,397,099'Semiconductor device having a plurality of fins and method for fabricating the same'20169,391,201'Source/drain structure and manufacturing the same'20169,362,386'FETs and methods for forming the same'20169,349,841'FinFETs and methods for forming the same'20169,318,367'FinFET structure with different fin heights and method for forming the same'20169,306,033'Semiconductor device and fabrication method thereof'20169,293,585'Semiconductor device structure and method of forming same'20169,281,307'Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure'20169,263,586'Quantum well fin-like field effect transistor (QWFinFET) having a two-section combo QW structure'20169,263,252'Method of protecting an interlayer dielectric layer and structure formed thereby'20169,257,558'FinFET device with gate oxide layer'20169,257,323'Semiconductor device and method for forming the same'20169,214,552'Method for fabricating a strain feature in a gate spacer of a semiconductor device'20159,209,280'Methods for doping fin field-effect transistors'20159,202,691'Semiconductor device having modified profile metal gate'20159,184,088'Method of making a shallow trench isolation (STI) structures'20159,171,762'Semiconductor device and fabrication method thereof'20159,159,604'Semiconductor device and method for forming the same'20159,159,552'Method of forming a germanium-containing FinFET'20159,153,695'Fin-last finFET and methods of forming same'20159,093,531'Fin structure of semiconductor device'20159,087,903'Buffer layer omega gate'20159,048,181'Mechanisms for forming ultra shallow junction'20158,987,791'FinFETs and methods for forming the same'20158,980,719'Methods for doping fin field-effect transistors'20158,963,251'Semiconductor device with strain technique'20158,946,035'Replacement channels for semiconductor devices and methods for forming the same using dopant concentration boost'20158,912,608'Semiconductor device and fabrication method thereof'20148,877,602'Mechanisms of doping oxide for forming shallow trench isolation'20148,828,813'Replacement channels'20148,809,175'Methods of anneal after deposition of gate layers'20148,809,139'Fin-last FinFET and methods of forming same'20148,796,666'MOS devices with strain buffer layer and methods of forming the same'20148,741,759'Method for fabricating a semiconductor device'20148,735,266'Mechanisms for forming ultra shallow junction'20148,592,915'Doped oxide for shallow trench isolation (STI)'20138,536,658'Mechanisms for forming ultra shallow junction'20138,461,015'STI structure and method of forming bottom void in same'20138,431,453'Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structure'20138,298,925'Mechanisms for forming ultra shallow junction'20128,278,196'High surface dopant concentration semiconductor device and method of fabricating'20128,187,928'Methods of forming integrated circuits'20127,834,389'Triangular space element for semiconductor device'20107,579,248'Resolving pattern-loading issues of SiGe stressor'20097,276,417'Hybrid STI stressor with selective re-oxidation anneal'20077,160,800'Decreasing metal-silicide oxidation during wafer queue time'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (45)· patent assignee history
2007–2020Based in Jhubei City, TW· patent location history
2012–2018Patents assigned to HUANG YU-LIEN (12)· patent assignee history
2012–2018Patents assigned to TSAI CHUN HSIUNG (8)· patent assignee history
2012–2018Patents assigned to WU CHII-MING (4)· patent assignee history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (68)· patent assignee history
2016–2020Based in Hsinchu County, TW· patent location history
2016–2020Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 68 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 45 | 2007–2016 |
| HUANG YU-LIENself | 12 | 2012–2018 |
| TSAI CHUN HSIUNG | 8 | 2012–2018 |
| WU CHII-MING | 4 | 2012–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jhubei City, TW | 88 | 2007–2020 |
| Hsinchu County, TW | 18 | 2016–2020 |
| Hsinchu, TW | 7 | 2016–2020 |