Inventor
Martin D. Giles
Inventor
Portland, OR, US
Overview
Patents· 31 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices40%
H01LSemiconductor devices17%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
B82YSpecific uses or applications of nanostructures12%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
C30BSingle-crystal growth4%
H10BElectronic memory devices1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,847,653Semiconductor device having metallic source and drain regions202010,636,871Silicon and silicon germanium nanowire structures202010,580,899Nanowire structures having non-discrete source and drain regions20209,806,193'Stress in trigate devices using complimentary gate fill materials'20179,680,013'Non-planar device having uniaxially strained semiconductor body and method of making same'20179,607,987'Methods for forming fins for metal oxide semiconductor device structures'20179,595,581'Silicon and silicon germanium nanowire structures'20179,583,487'Semiconductor device having metallic source and drain regions'20179,564,522'Nanowire structures having non-discrete source and drain regions'20179,450,092'Stress in trigate devices using complimentary gate fill materials'20169,224,754'Stress in trigate devices using complimentary gate fill materials'20159,129,829'Silicon and silicon germanium nanowire structures'20159,087,863'Nanowire structures having non-discrete source and drain regions'20158,753,942'Silicon and silicon germanium nanowire structures'20148,741,733'Stress in trigate devices using complimentary gate fill materials'20148,558,279'Non-planar device having uniaxially strained semiconductor body and method of making same'20138,487,348'Methods and apparatus to reduce layout based strain variations in non-planar transistor structures'20138,362,566'Stress in trigate devices using complimentary gate fill materials'20138,269,283'Methods and apparatus to reduce layout based strain variations in non-planar transistor structures'20127,838,373'Replacement spacers for MOSFET fringe capacitance reduction and processes of making same'20107,719,057'Multiple oxide thickness for a semiconductor device'20107,679,145'Transistor performance enhancement using engineered strains'20107,473,614'Method for manufacturing a silicon-on-insulator (SOI) wafer with an etch stop layer'20097,470,972'Complementary metal oxide semiconductor integrated circuit using uniaxial compressive stress and biaxial compressive stress'20087,452,764'Gate-induced strain for MOS performance improvement'20087,091,560'Method and structure to decrease area capacitance within a buried insulator device'20066,982,433'Gate-induced strain for MOS performance improvement'20066,872,455'Semiconductor material and method for enhancing solubility of a dopant therein'20056,867,104'Method to form a structure to decrease area capacitance within a buried insulator device'20056,617,228'Semiconductor material and method for enhancing solubility of a dopant therein'20036,498,078'Method for enhancing the solubility of boron and indium in silicon'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2005Based in Hillsborough, OR, US· patent location history
2005–2020Patents assigned to INTEL CORP (28)· patent assignee history
2005–2020Based in Portland, OR, US· patent location history
2006–2008Based in Hillsboro, OR, US· patent location history
2012–2017Patents assigned to GILES MARTIN D (9)· patent assignee history
2012–2017Patents assigned to CEA STEPHEN M (7)· patent assignee history
2012–2015Patents assigned to KAVALIEROS JACK T (6)· patent assignee history
2014–2017Patents assigned to CAPPELLANI ANNALISA (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 28 | 2005–2020 |
| GILES MARTIN Dself | 9 | 2012–2017 |
| CEA STEPHEN M | 7 | 2012–2017 |
| KAVALIEROS JACK T | 6 | 2012–2015 |
| CAPPELLANI ANNALISA | 5 | 2014–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 26 | 2005–2020 |
| Hillsborough, OR, US | 3 | 2002–2005 |
| Hillsboro, OR, US | 2 | 2006–2008 |