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Inventor

Hermann Ruckerbauer

Inventor
Moos, DE

Overview

65→
Patents
2002–2014
Patent span
Physics
Primary field (CPC G)

Patents· 65 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores50%
G06FElectric digital data processing21%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H01RElectrically-conductive connections3%
H05KPrinted circuits3%
H03KPulse technique2%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
G01RMeasuring electric variables1%
PatentTitleYear
8,914,589'Multi-port DRAM architecture for accessing different memory partitions'20148,547,767'Chip, multi-chip system in a method for performing a refresh of a memory array'20138,495,310'Method and system including plural memory controllers and a memory access control bus for accessing a memory device'20138,334,599'Electronic device having a chip stack'20128,271,827'Memory system with extended memory density capability'20128,183,676'Memory circuit having memory chips parallel connected to ports and corresponding production method'20128,161,219'Distributed command and address bus architecture for a memory module having portions of bus lines separately disposed'20128,144,755'Method and apparatus for determining a skew'20128,120,958'Multi-die memory, apparatus and multi-die memory stack'20128,041,865'Bus termination system and method'20118,015,438'Memory circuit'20117,986,582'Method of operating a memory apparatus, memory device and memory apparatus'20117,957,209'Method of operating a memory apparatus, memory device and memory apparatus'20117,956,665'Methods and articles of manufacture for operating electronic devices on a plurality of clock signals'20117,928,525'Integrated circuit with wireless connection'20117,920,433'Method and apparatus for storage device with a logic unit and method for manufacturing same'20117,848,153'High speed memory architecture'20107,831,797'Memory system and method for transferring data therein'20107,796,446'Memory dies for flexible use and method for configuring memory dies'20107,771,206'Horizontal dual in-line memory modules'20107,768,857'Method of refreshing data in a storage location based on heat dissipation level and system thereof'20107,698,470'Integrated circuit, chip stack and data processing system'20107,650,457'Memory module comprising a plurality of memory devices'20107,638,869'Semiconductor device'20097,560,807'Arrangement of semiconductor memory devices and semiconductor memory module comprising an arrangement of semiconductor memory devices'20097,519,894'Memory device with error correction code module'20097,477,717'Input receiver circuit'20097,475,187'High-speed interface circuit for semiconductor memory chips and memory system including the same'20097,447,805'Buffer chip and method for controlling one or more memory arrangements'20087,439,615'Semiconductor component comprising an integrated semiconductor chip and a chip housing, and electronic device'20087,414,917'Re-driving CAwD and rD signal lines'20087,411,843'Semiconductor memory arrangement with branched control and address bus'20087,404,136'Semiconductor memory device including a signal control device and method of operating the same'20087,397,684'Semiconductor memory array with serial control/address bus'20087,386,696'Semiconductor memory module'20087,383,416'Method for setting a second rank address from a first rank address in a memory module'20087,376,802'Memory arrangement'20087,362,622'System for determining a reference level and evaluating a signal on the basis of the reference level'20087,342,815'DQS signaling in DDR-III memory systems without preamble'20087,339,840'Memory system and method of accessing memory chips of a memory system'20087,334,150'Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals'20087,293,151'Memory system and method for transferring data therein'20077,275,189'Memory module and method for operating a memory module in a data memory system'20077,224,636'Semiconductor memory module'20077,222,271'Method for repairing hardware faults in memory chips'20077,180,821'Memory device, memory controller and memory system having bidirectional clock lines'20077,173,877'Memory system with two clock lines and a memory device'20077,078,793'Semiconductor memory module'20067,061,784'Semiconductor memory module'20067,050,340'Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system'20067,043,653'Method and apparatus for synchronous signal transmission between at least two logic or memory components'20067,042,206'Integrated circuit and method for operating the integrated circuit'20067,009,848'Method, adapter card and configuration for an installation of memory modules'20066,972,981'Semiconductor memory module'20056,958,613'Method for calibrating semiconductor devices using a common calibration reference and a calibration circuit'20056,918,778'Configuration, plug-in mount and contact element for fixing and contacting switching assemblies on a substrate'20056,896,534'Zero insertion force mount for fixing and making contact with circuit subassemblies on a substrate'20056,840,808'Connector for a plurality of switching assemblies with compatible interfaces'20056,819,625'Memory device'20046,765,826'Write protection control for electronic assemblies'20046,724,685'Configuration for data transmission in a semiconductor memory system, and relevant data transmission method'20046,677,813'Integrated circuit for receiving a clock signal, particularly for a semiconductor memory circuit'20046,636,097'Method and input circuit for evaluating a data signal at an input of a memory component'20036,438,057'DRAM refresh timing adjustment device, system and method'20026,417,722'Sense amplifier configuration having a field-effect transistor having a short channel length and an adjustable threshold voltage'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2014Patents assigned to INFINEON TECHNOLOGIES AG (39)· patent assignee history
2002–2014Based in Moos, DE· patent location history
2004Based in Moss, DE· patent location history
2008–2013Patents assigned to QIMONDA AG (24)· patent assignee history
2012–2014Patents assigned to RUCKERBAUER HERMANN (9)· patent assignee history
2012–2014Patents assigned to GREGORIUS PETER (6)· patent assignee history
2012–2014Patents assigned to STECKER JOHANNES (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
INFINEON TECHNOLOGIES AG392002–2014
QIMONDA AG242008–2013
RUCKERBAUER HERMANNself92012–2014
GREGORIUS PETER62012–2014
STECKER JOHANNES62012–2014
Locations
LocationPatentsSpan
Moos, DE642002–2014
Moss, DE12004