Inventor
Nidhi NIDHI
Inventor
US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices34%
H10DInorganic electric semiconductor devices34%
B82YSpecific uses or applications of nanostructures10%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
H03DDemodulation or transference of modulation from one carrier to another1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,568,682Nanoribbon thick gate device with hybrid dielectric tuning for high breakdown and VT modulation202612,453,145Single gated 3D nanowire inverter for high density thick gate SoC applications202512,369,358Co-integrated high performance nanoribbon transistors with high voltage thick gate finFET devices202512,349,411Gate-all-around integrated circuit structures having dual nanoribbon channel structures202512,249,622Nanoribbon thick gate devices with differential ribbon spacing and width for SOC applications202512,148,757Integration of Si-based transistors with non-Si technologies by semiconductor regrowth over an insulator material202412,040,395High voltage extended-drain MOS (EDMOS) nanowire transistors202412,027,613III-N transistor arrangements for reducing nonlinearity of off-state capacitance202411,996,403ESD diode solution for nanoribbon architectures202411,881,511Superlattice FINFET with tunable drive current capability202411,862,703Gate-all-around integrated circuit structures having dual nanoribbon channel structures202411,848,362III-N transistors with contacts of modified widths202311,830,818Semiconductor device having metal interconnects with different thicknesses202311,791,380Single gated 3D nanowire inverter for high density thick gate SOC applications202311,757,027E-D mode 2DEG FET with gate spacer to locally tune VT and improve breakdown202311,737,362Harvesting energy in an integrated circuit using the seebeck effect202311,715,790Charge-induced threshold voltage tuning in III-N transistors202311,688,788Transistor gate structure with hybrid stacks of dielectric material202311,670,709III-N transistors with local stressors for threshold voltage control202311,658,217Transistors with ion- or fixed charge-based field plate structures202311,652,143III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics202311,626,513Antenna gate field plate on 2DEG planar FET202311,610,971Cap layer on a polarization layer to preserve channel sheet resistance202311,588,037Planar transistors with wrap-around gates and wrap-around source and drain contacts202311,587,924Integration of passive components in III-N devices202311,581,313Integration of III-N transistors and non-III-N transistors by semiconductor regrowth202311,527,532Enhancement-depletion cascode arrangements for enhancement mode III-N transistors202211,502,191Transistors with backside field plate structures202211,450,617Transmission line structures for III-N devices202211,437,483Gate-all-around integrated circuit structures having dual nanoribbon channel structures202211,387,328III-N tunnel device architectures and high frequency mixers employing a III-N tunnel device202211,264,329Semiconductor device having metal interconnects with different thicknesses2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to INTEL CORP (32)· patent assignee history
2022–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 32 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 32 | 2022–2026 |