LexDanaLexDanabeta
Inventor

Jean Y. Yang

Inventor
Sunnyvale, CA, US

Overview

68→
Patents
1999–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 68 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Bprimary
H10BElectronic memory devices36%
H10DInorganic electric semiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests7%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
G11CStatic stores4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
B82YSpecific uses or applications of nanostructures1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
G02FOptical devices or arrangements for the control of light by modification of the optical properties of the media of the elements involved therein1%
PatentTitleYear
9,318,333'Dielectric extension to mitigate short channel effects'20168,673,716'Memory manufacturing process with bitline isolation'20148,415,734'Memory device protection layer'20138,404,541'Strapping contact for charge protection'20137,977,218'Thin oxide dummy tiling as charge protection'20117,750,407'Strapping contact for charge protection'20107,696,094'Method for improved planarization in semiconductor devices'20107,553,727'Using implanted poly-1 to improve charging protection in dual-poly process'20097,432,178'Bit line implant'20087,307,027'Void free interlayer dielectric'20077,163,860'Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device'20077,115,469'Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process'20067,098,546'Alignment marks with salicided spacers between bitlines for alignment signal improvement'20067,078,749'Memory structure having tunable interlayer dielectric and method for fabricating same'20067,052,961'Method for forming wordlines having irregular spacing in a memory array'20067,033,957'ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices'20067,023,046'Undoped oxide liner/BPSG for improved data retention'20067,018,868'Disposable hard mask for memory bitline scaling'20066,994,939'Semiconductor manufacturing resolution enhancement system and method for simultaneously patterning different feature types'20066,989,563'Flash memory cell with UV protective layer'20066,989,320'Bitline implant utilizing dual poly'20066,987,048'Memory device having silicided bitlines and method of forming the same'20066,969,886'ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices'20056,955,965'Process for fabrication of nitride layer with reduced hydrogen content in ONO structure in semiconductor device'20056,949,481'Process for fabrication of spacer layer with reduced hydrogen content in semiconductor device'20056,933,219'Tightly spaced gate formation through damascene process'20056,927,145'Bitline hard mask spacer flow for memory cell scaling'20056,897,533'Multi-bit silicon nitride charge-trapping non-volatile memory cell'20056,884,681'Method of manufacturing a semiconductor memory with deuterated materials'20056,869,844'Method and structure for protecting NROM devices from induced charge damage during device fabrication'20056,855,608'Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance'20056,803,275'ONO fabrication process for reducing oxygen vacancy content in bottom oxide layer in flash memory devices'20046,797,565'Methods for fabricating and planarizing dual poly scalable SONOS flash memory'20046,767,791'Structure and method for suppressing oxide encroachment in a floating gate memory cell'20046,765,254'Structure and method for preventing UV radiation damage and increasing data retention in memory cells'20046,754,106'Reference cell with various load circuits compensating for source side loading effects in a non-volatile memory'20046,744,105'Memory array having shallow bit line with silicide contact portion and method of formation'20046,737,701'Structure and method for reducing charge loss in a memory cell'20046,720,133'Memory manufacturing process using disposable ARC for wordline formation'20046,706,595'Hard mask process for memory device without bitline shorts'20046,707,078'Dummy wordline for erase and bitline leakage'20046,680,509'Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory'20046,670,241'Semiconductor memory with deuterated materials'20036,667,212'Alignment system for planar charge trapping dielectric memory cell lithography'20036,653,191'Memory manufacturing process using bitline rapid thermal anneal'20036,653,190'Flash memory with controlled wordline width'20036,627,887'System and method for constructing a profile of a structure in an integrated circuit'20036,620,717'Memory with disposable ARC for wordline formation'20036,617,215'Memory wordline hard mask'20036,555,436'Simultaneous formation of charge storage and bitline to wordline isolation'20036,541,816'Planar structure for non-volatile memory devices'20036,500,768'Method for selective removal of ONO layer'20026,479,348'Method of making memory wordline hard mask extension'20026,468,865'Method of simultaneous formation of bitline isolation and periphery oxide'20026,465,306'Simultaneous formation of charge storage and bitline to wordline isolation'20026,445,030'Flash memory erase speed by fluorine implant or fluorination'20026,440,797'Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory'20026,441,398'Algorithm for detecting sloped contact holes using a critical-dimension waveform'20026,436,768'Source drain implant during ONO formation for improved isolation of SONOS devices'20026,417,082'Semiconductor structure'20026,403,420'Nitrogen implant after bit-line formation for ONO flash memory devices'20026,399,984'Species implantation for minimizing interface defect density in flash memory devices'20026,395,654'Method of forming ONO flash memory devices using rapid thermal oxidation'20026,362,051'Method of forming ONO flash memory devices using low energy nitrogen implantation'20026,284,600'Species implantation for minimizing interface defect density in flash memory devices'20016,277,661'Method for detecting sloped contact holes using a critical-dimension waveform'20015,888,898'HSQ baking for reduced dielectric constant'19995,888,911'HSQ processing for reduced dielectric constant'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2010Patents assigned to ADVANCED MICRO DEVICES INC (49)· patent assignee history
1999–2002Based in Palo Alto, CA, US· patent location history
2002–2004Patents assigned to FUJITSU LTD (16)· patent assignee history
2002–2014Based in Sunnyvale, CA, US· patent location history
2004–2006Patents assigned to FASL LLC (8)· patent assignee history
2006–2014Patents assigned to SPANSION LLC (13)· patent assignee history
2009–2016Based in Glendale, CA, US· patent location history
2013–2016Patents assigned to YANG JEAN YEE-MEI (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ADVANCED MICRO DEVICES INC491999–2010
FUJITSU LTD162002–2004
SPANSION LLC132006–2014
FASL LLC82004–2006
YANG JEAN YEE-MEIself22013–2016
Locations
LocationPatentsSpan
Sunnyvale, California, US552002–2014
Glendale, California, US72009–2016
Palo Alto, California, US61999–2002