Inventor
Yiming Gu
Inventor
Hillsboro, OR, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G03Fprimary
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices19%
H10DInorganic electric semiconductor devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
B05BSpraying apparatus2%
G02BOptical elements, systems or apparatus2%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,424,654Power device with high aspect ratio trench contacts and submicron pitches between trenches201910,020,380Power device with high aspect ratio trench contacts and submicron pitches between trenches20189,865,694'Split-gate trench power mosfet with protected shield oxide'20189,741,808'Split-gate trench power MOSFET with protected shield oxide'20179,679,822'Method for monitoring epitaxial growth geometry shift'20179,421,567'Recycle photochemical to reduce cost of material and environmental impact'20169,323,163'Cylindrical reticle system, exposure apparatus and exposure method'20169,298,099'Exposure apparatus and exposure method thereof'20169,281,368'Split-gate trench power MOSFET with protected shield oxide'20169,223,229'Exposure device and exposure method'20159,134,624'Lithography machine and scanning and exposing method thereof'20159,081,149'Method, optical module and auto-focusing system for wafer edge exposure'20159,070,557'Method of forming double pattern in a structure'20158,982,314'Photolithographic apparatus'20158,853,093'Method for forming double patterned structure'20148,304,317'Gate line edge roughness reduction by using 2P/2E process together with high temperature bake'20127,349,752'Dynamically coupled metrology and lithography'20087,235,336'Method for determining photoresist thickness and structure formed using determined photoresist thickness'20077,129,149'Method for forming shallow trench isolation structure with anti-reflective liner'20066,913,872'Dual-wavelength exposure for reduction of implant shadowing'20056,797,456'Dual-layer deep ultraviolet photoresist process and structure'20046,733,936'Method for generating a swing curve and photoresist feature formed using swing curve'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2008Patents assigned to INTEGRATED DEVICE TECH (6)· patent assignee history
2004–2019Based in Hillsboro, OR, US· patent location history
2012–2016Patents assigned to GU YIMING (4)· patent assignee history
2012Based in Binhai New Area, CN· patent location history
2014–2015Patents assigned to SEMICONDUCTOR MFG INT CORP (4)· patent assignee history
2014–2016Based in Shanghai, CN· patent location history
2015Based in Beijing, CN· patent location history
2016–2019Patents assigned to ALPHA & OMEGA SEMICONDUCTOR (7)· patent assignee history
2018–2019Patents assigned to ALPHA & OMEGA SEMICONDUCTOR INCORPORATED (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALPHA & OMEGA SEMICONDUCTOR | 7 | 2016–2019 |
| INTEGRATED DEVICE TECH | 6 | 2004–2008 |
| GU YIMINGself | 4 | 2012–2016 |
| SEMICONDUCTOR MFG INT CORP | 4 | 2014–2015 |
| ALPHA & OMEGA SEMICONDUCTOR INCORPORATED | 2 | 2018–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 13 | 2004–2019 |
| Shanghai, CN | 6 | 2014–2016 |
| Beijing, CN | 2 | 2015 |
| Binhai New Area, CN | 1 | 2012 |