Inventor
Chia-Hong Jan
Inventor
Portland, OR, US
Overview
Patents· 122 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices34%
H01LSemiconductor devices22%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10BElectronic memory devices3%
G11CStatic stores2%
C23CCoating metallic material1%
B82YSpecific uses or applications of nanostructures1%
G02BOptical elements, systems or apparatus1%
PatentTitleYear
11,121,040Multi voltage threshold transistors through process and design-induced multiple work functions202111,114,538Transistor with an airgap spacer adjacent to a transistor gate202111,075,286Hybrid finfet structure with bulk source/drain regions202110,964,690Resistor between gates in self-aligned gate edge architecture202110,950,606Dual fin endcap for self-aligned gate edge (SAGE) architectures202110,930,729Fin-based thin film resistor202110,923,574Transistor with inner-gate spacer202110,903,372Metal-oxide-polysilicon tunable resistor for flexible circuit design and method of fabricating same202110,892,192Non-planar I/O and logic semiconductor devices having different workfunction on common substrate202110,892,261Metal resistor and self-aligned gate edge (SAGE) architecture having a metal resistor202110,854,607Isolation well doping with solid-state diffusion sources for finFET architectures202010,854,757FINFET based junctionless wrap around structure202010,847,544High voltage three-dimensional devices having dielectric liners202010,847,456Antifuse element using spacer breakdown202010,811,751Monolithic splitter using re-entrant poly silicon waveguides202010,784,378Ultra-scaled fin pitch having dual gate dielectrics202010,763,209MOS antifuse with void-accelerated breakdown202010,761,264Transmission lines using bending fins from local stress202010,756,210Depletion mode gate in ultrathin FINFET based architecture202010,741,640Dielectric and isolation lower Fin material for Fin-based electronics202010,707,346High-voltage transistor with self-aligned isolation202010,692,771Non-planar I/O and logic semiconductor devices having different workfunction on common substrate202010,692,888High voltage three-dimensional devices having dielectric liners202010,658,361Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process202010,643,999Doping with solid-state diffusion sources for finFET architectures202010,559,688Transistor with thermal performance boost202010,535,747Transistor with dual-gate spacer202010,431,661Transistor with inner-gate spacer201910,355,081Dielectric and isolation lower Fin material for Fin-based electronics201910,355,093Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same201910,340,273Doping with solid-state diffusion sources for finFET architectures201910,340,220Compound lateral resistor structures for integrated circuitry201910,312,367Monolithic integration of high voltage transistors and low voltage non-planar transistors201910,304,681Dual height glass for finFET doping201910,263,112Vertical non-planar semiconductor device for system-on-chip (SoC) applications201910,243,034Pillar resistor structures for integrated circuitry201910,229,853Non-planar I/O and logic semiconductor devices having different workfunction on common substrate201910,204,999Transistor with airgap spacer201910,192,969Transistor gate metal with laterally graduated work function201910,164,115Non-linear fin-based devices201810,158,034Through silicon via based photovoltaic cell201810,115,721Planar device on fin-based transistor architecture201810,096,599Methods of integrating multiple gate dielectric transistors on a tri-gate (finFET) process201810,090,304Isolation well doping with solid-state diffusion sources for FinFET architectures201810,020,313Antifuse with backfilled terminals201810,008,445Embedded fuse with conductor backfill201810,002,954Fin-based semiconductor devices and methods20189,972,642High voltage three-dimensional devices having dielectric liners20189,972,616Methods of forming tuneable temperature coefficient FR embedded resistors20189,947,585Multi-gate transistor with variably sized fin20189,929,090'Antifuse element using spacer breakdown'20189,911,815'Extended-drain structures for high voltage field effect transistors'20189,899,472'Dielectric and isolation lower fin material for fin-based electronics'20189,881,927'CMOS-compatible polycide fuse structure and method of fabricating same'20189,865,695'High-voltage transistor architectures, processes of forming same, and systems containing same'20189,842,944'Solid-source diffused junction for fin-based electronics'20179,806,095'High voltage three-dimensional devices having dielectric liners'20179,799,668'Memory cell having isolated charge sites and method of fabricating same'20179,793,373'Field effect transistor structure with abrupt source/drain junctions'20179,786,783'Transistor architecture having extended recessed spacer and source/drain regions and method of making same'20179,780,217'Non-planar semiconductor device having self-aligned fin with top blocking layer'20179,748,252'Antifuse element utilizing non-planar topology'20179,748,327'Pillar resistor structures for integrated circuitry'20179,741,721'Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)'20179,640,634'Field effect transistor structure with abrupt source/drain junctions'20179,570,467'High voltage three-dimensional devices having dielectric liners'20179,520,494'Vertical non-planar semiconductor device for system-on-chip (SoC) applications'20169,356,023'Planar device on fin-based transistor architecture'20169,324,665'Metal fuse by topology'20169,159,734'Antifuse element utilizing non-planar topology'20158,993,401'High-voltage transistor architectures, processes of forming same, and systems containing same'20158,981,481'High voltage three-dimensional devices having dielectric liners'20158,889,508'Precision resistor for non-planar semiconductor device architecture'20148,796,772'Precision resistor for non-planar semiconductor device architecture'20148,741,720'Penetrating implant for forming a semiconductor device'20148,681,573'Programmable/re-programmable device in high-k metal gate MOS'20148,669,617'Multi-gate transistors'20148,487,376'High-voltage transistor architectures, processes of forming same, and systems containing same'20138,432,751'Memory cell using BTI effects in high-k metal gate MOS'20138,426,927'Penetrating implant for forming a semiconductor device'20138,174,060'Selective spacer formation on transistors of different classes on the same device'20128,154,067'Selective spacer formation on transistors of different classes on the same device'20128,101,471'Method of forming programmable anti-fuse element'20127,943,468'Penetrating implant for forming a semiconductor device'20117,691,718'Dual layer hard mask for block salicide poly resistor (BSR) patterning'20107,682,916'Field effect transistor structure with abrupt source/drain junctions'20107,560,780'Active region spacer for semiconductor devices and method to form the same'20097,541,239'Selective spacer formation on transistors of different classes on the same device'20097,436,035'Method of fabricating a field effect transistor structure with abrupt source/drain junctions'20087,338,873'Method of fabricating a field effect transistor structure with abrupt source/drain junctions'20087,211,872'Device having recessed spacers for improved salicide resistance on polysilicon gates'20077,115,502'Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process'20067,071,129'Enhancing adhesion of silicon nitride films to carbon-containing oxide films'20066,887,762'Method of fabricating a field effect transistor structure with abrupt source/drain junctions'20056,861,758'Structure and manufacturing process of localized shunt to reduce electromigration failure of copper dual damascene process'20056,777,760'Device with recessed thin and thick spacers for improved salicide resistance on polysilicon gates'20046,777,759'Device structure and method for reducing silicide encroachment'20046,765,273'Device structure and method for reducing silicide encroachment'20046,703,672'Polysilicon/amorphous silicon composite gate electrode'20046,593,633'Method and device for improved salicide resistance on polysilicon gates'20036,521,964'Device having spacers for improved salicide resistance on polysilicon gates'20036,518,155'Device structure and method for reducing silicide encroachment'20036,509,618'Device having thin first spacers and partially recessed thick second spacers for improved salicide resistance on polysilicon gates'20036,506,652'Method of recessing spacers to improved salicide resistance on polysilicon gates'20036,479,391'Method for making a dual damascene interconnect using a multilayer hard mask'20026,326,664'Transistor with ultra shallow tip and method of fabrication'20016,271,096'Method and device for improved salicide resistance on polysilicon gates'20016,268,254'Method and device for improved salicide resistance on polysilicon gates'20016,251,762'Method and device for improved salicide resistance on polysilicon gates'20016,235,598'Method of using thick first spacers to improve salicide resistance on polysilicon gates'20016,235,568'Semiconductor device having deposited silicon regions and a method of fabrication'20016,198,142'Transistor with minimal junction capacitance and method of fabrication'20016,188,117'Method and device for improved salicide resistance on polysilicon gates'20016,165,826'Transistor with low resistance tip and method of fabrication in a CMOS process'20006,121,100'Method of fabricating a MOS transistor with a raised source/drain extension'20006,114,722'Microcrystalline silicon structure and fabrication process'20006,017,819'Method for forming a polysilicon/amorphous silicon composite gate electrode'20005,908,313'Method of forming a transistor'19995,891,809'Manufacturable dielectric formed using multiple oxidation and anneal steps'19995,885,884'Process for fabricating a microcrystalline silicon structure'19995,710,450'Transistor with ultra shallow tip and method of fabrication'19985,516,725'Process for preparing schottky diode contacts with predetermined barrier heights'1996Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1996–2021Based in Portland, OR, US· patent location history
1998–2021Patents assigned to INTEL CORP (121)· patent assignee history
2012–2020Patents assigned to HAFEZ WALID M (14)· patent assignee history
2012–2017Patents assigned to JAN CHIA-HONG (14)· patent assignee history
2012Based in Beaverton, OR, US· patent location history
2014–2020Patents assigned to PARK JOODONG (7)· patent assignee history
2014–2020Patents assigned to TSAI CURTIS (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 121 | 1998–2021 |
| HAFEZ WALID M | 14 | 2012–2020 |
| JAN CHIA-HONGself | 14 | 2012–2017 |
| PARK JOODONG | 7 | 2014–2020 |
| TSAI CURTIS | 7 | 2014–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 121 | 1996–2021 |
| Beaverton, OR, US | 1 | 2012 |