Inventor
Kevin G. Duesman
Inventor
Boise, ID, US
Overview
Patents· 140 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10DInorganic electric semiconductor devices12%
H10BElectronic memory devices8%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G01RMeasuring electric variables5%
H05KPrinted circuits4%
H01LSemiconductor devices4%
B29CShaping or joining of plastics2%
B29KIndexing scheme associated with subclasses b29b, b29c or b29d, relating to moulding materials or to materials for moulds, reinforcements, fillers or preformed parts, e.g. inserts2%
PatentTitleYear
11,056,467Semiconductor devices with through silicon vias and package-level configurability202110,930,645Semiconductor devices with package-level configurability202110,867,991Semiconductor devices with package-level configurability202010,811,372Semiconductor devices with post-probe configurability202010,784,192Semiconductor devices having 3-dimensional inductive structures202010,580,767Semiconductor devices with package-level configurability202010,483,241Semiconductor devices with through silicon vias and package-level configurability201910,453,829Method and apparatus for reducing capacitance of input/output pins of memory device201910,403,585Semiconductor devices with post-probe configurability201910,312,232Semiconductor devices with package-level configurability201910,283,462Semiconductor devices with post-probe configurability201910,128,229Semiconductor devices with package-level configurability20188,541,836'Recessed access device for a memory'20138,431,980'Random access memory device utilizing a vertically oriented select transistor'20138,319,280'Recessed access device for a memory'20128,035,160'Recessed access device for a memory'20117,777,264'Random access memory device utilizing a vertically oriented select transistor'20107,730,372'Device and method for testing integrated circuit dice in an integrated circuit module'20107,646,016'Method for automated testing of the modulation transfer function in image sensors'20107,645,671'Recessed access device for a memory'20107,519,881'Device and method for testing integrated circuit dice in an integrated circuit module'20097,375,793'Apparatus for photolithographic processing'20087,336,522'Apparatus and method to reduce undesirable effects caused by a fault in a memory device'20087,276,754'Annular gate and technique for fabricating an annular gate'20077,215,361'Method for automated testing of the modulation transfer function in image sensors'20077,208,758'Dynamic integrated circuit clusters, modules including same and methods of fabricating'20077,205,598'Random access memory device utilizing a vertically oriented select transistor'20077,142,446'Apparatus and method to reduce undesirable effects caused by a fault in a memory device'20067,128,551'Surface smoothing of stereolithographically formed 3-D objects'20067,081,385'Nanotube semiconductor devices and methods for making the same'20067,063,524'Apparatus for increased dimensional accuracy of 3-D object creation'20067,034,560'Device and method for testing integrated circuit dice in an integrated circuit module'20066,954,385'Method and apparatus for sensing resistive memory state'20056,951,789'Method of fabricating a random access memory device utilizing a vertically oriented select transistor'20056,946,863'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'20056,893,804'Surface smoothing of stereolithographically formed 3-D objects'20056,872,509'Apparatus and methods for photolithographic processing'20056,858,891'Nanotube semiconductor devices and methods for making the same'20056,841,438'Annular gate and technique for fabricating an annular gate'20056,801,048'Device and method for testing integrated circuit dice in an integrated circuit module'20046,797,545'Method and apparatus for fabricating electronic device'20046,794,699'Annular gate and technique for fabricating an annular gate'20046,791,885'Programmable conductor random access memory and method for sensing same'20046,787,400'Electrostatic discharge protection device having a graded junction and method for forming the same'20046,740,476'Surface smoothing of stereolithographically formed 3-D objects'20046,731,528'Dual write cycle programmable conductor memory system and method of operation'20046,713,788'Opto-electric mounting apparatus'20046,709,795'Stereolithographically packaged, in-process semiconductor die'20046,707,673'Heat sink for chip stacking applications'20046,673,707'Method of forming semiconductor device utilizing die active surfaces for laterally extending die internal and external connections'20046,664,632'Utilization of die active surfaces for laterally extending die internal and external connections'20036,632,343'Method and apparatus for electrolytic plating of surface metals'20036,633,180'Methods of rerouting dies using antifuses'20036,633,183'Antifuse reroute of dies'20036,618,304'Memory module with test mode'20036,605,956'Device and method for testing integrated circuit dice in an integrated circuit module'20036,593,218'Electrostatic discharge protection device having a graded junction and method for forming the same'20036,576,960'Electrostatic discharge protection device having a graded junction and method for forming the same'20036,562,278'Methods of fabricating housing structures and micromachines incorporating such structures'20036,544,465'Method for forming three dimensional structures from liquid with improved surface finish'20036,541,850'Utilization of die active surfaces for laterally extending die internal and external connections'20036,531,345'Method and apparatus for fabricating electronic device'20036,515,325'Nanotube semiconductor devices and methods for making the same'20036,514,787'Opto-electric mounting apparatus'20036,482,576'Surface smoothing of stereolithographically formed 3-D objects'20026,475,851'Circuit for providing isolation of integrated circuit active areas'20026,466,053'Antifuse reroute of dies'20026,448,628'Chip decoupling capacitor'20026,449,161'Heat sink for chip stacking applications'20026,417,695'Antifuse reroute of dies'20026,408,508'Method for making flexible trace surface circuit board'20026,381,184'Method and apparatus for rapidly testing memory devices'20026,380,563'Opto-electric mounting apparatus'20026,365,937'Electrostatic discharge protection device having a graded junction'20026,362,532'Semiconductor device having ball-bonded pads'20026,356,474'Efficient open-array memory device architecture and method'20026,355,508'Method for forming electrostatic discharge protection device having a graded junction'20026,331,736'Utilization of die repattern layers for die internal connections'20016,326,245'Method and apparatus for fabricating electronic device'20016,319,756'Heat sink for chip stacking applications'20016,242,782'Circuit for providing isolation of integrated circuit active areas'20016,240,535'Device and method for testing integrated circuit dice in an integrated circuit module'20016,230,292'Devices and method for testing cell margin of memory devices'20016,229,296'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'20016,217,232'Method and apparatus for aligning an optic fiber with an opto-electronic device'20016,201,695'Heat sink for chip stacking applications'20016,184,568'Integrated circuit module having on-chip surge capacitors'20016,169,695'Method and apparatus for rapidly testing memory devices'20016,124,163'Integrated chip multiplayer decoupling capacitors'20006,124,625'Chip decoupling capacitor'20006,124,195'Utilization of die repattern layers for die internal connections'20006,117,696'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'20006,105,152'Devices and methods for testing cell margin of memory devices'20006,093,933'Method and apparatus for fabricating electronic device'20006,088,282'System and method for an antifuse bank'20006,078,100'Utilization of die repattern layers for die internal connections'20006,043,564'Semiconductor device having ball-bonded pads'20006,031,727'Printed circuit board with integrated heat sink'20006,015,729'Integrated chip multilayer decoupling capcitors'20006,002,590'Flexible trace surface circuit board and method for making flexible trace surface circuit board'19995,991,904'Method and apparatus for rapidly testing memory devices'19995,986,409'Flat panel display and method of its manufacture'19995,986,916'On-chip program voltage generator for antifuse repair'19995,977,763'Circuit and method for measuring and forcing an internal voltage of an integrated circuit'19995,956,275'Memory-cell array and a method for repairing the same'19995,953,216'Method and apparatus for replacing a defective integrated circuit device'19995,949,730'Method and apparatus for quickly restoring digit I/O lines'19995,936,908'System and method for an antifuse bank'19995,920,516'Circuit and method for enabling a function in a multiple memory device module'19995,889,307'Sacrificial discharge device'19995,872,740'System and method for an antifuse bank'19995,834,820'Circuit for providing isolation of integrated circuit active areas'19985,824,569'Semiconductor device having ball-bonded pads'19985,825,697'Circuit and method for enabling a function in a multiple memory device module'19985,796,746'Device and method for testing integrated circuit dice in an integrated circuit module'19985,796,666'Method and apparatus for quickly restoring digit I/O lines'19985,790,448'On-chip program voltage generator for antifuse repair'19985,787,044'Memory-cell array and a method for repairing the same'19985,764,574'Method and apparatus for back-end repair of multi-chip modules'19985,758,063'Testing mapped signal sources'19985,739,576'Integrated chip multilayer decoupling capacitors'19985,740,111'Charge pump disablement apparatus'1998RE035764'Inverting output driver circuit for reducing electron injection into the substrate'19985,724,282'System and method for an antifuse bank'19985,687,109'Integrated circuit module having on-chip surge capacitors'19975,677,878'Method and apparatus for quickly restoring digit I/O lines'19975,604,693'On-chip program voltage generator for antifuse repair'19975,539,347'Memory device initialization'19965,522,038'Testing mapped signal sources'19965,416,363'Logic circuit initialization'19955,347,179'Inverting output driver circuit for reducing electron injection into the substrate'19945,324,681'Method of making a 3-dimensional programmable antifuse for integrated circuits'19945,307,309'Memory module having on-chip surge capacitors'19945,301,143'Method for identifying a semiconductor die using an IC with programmable links'19945,266,821'Chip decoupling capacitor'19935,245,577'Integrated circuit two-cycle test mode activation circuit'19935,214,657'Method for fabricating wafer-scale integration wafers and method for utilizing defective wafer-scale integration wafers'19935,110,754'Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM'19925,059,899'Semiconductor dies and wafers and methods for making'19915,032,892'Depletion mode chip decoupling capacitor'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2021Patents assigned to MICRON TECHNOLOGY INC (133)· patent assignee history
1991–2021Based in Boise, ID, US· patent location history
1994–1995Patents assigned to MICRON SEMICONDUCTOR INC (3)· patent assignee history
2012–2013Patents assigned to DUESMAN KEVIN G (2)· patent assignee history
2012Patents assigned to BEIGEL KURT D (1)· patent assignee history
2013Patents assigned to BISSEY LUCIEN J (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 133 | 1991–2021 |
| MICRON SEMICONDUCTOR INC | 3 | 1994–1995 |
| DUESMAN KEVIN Gself | 2 | 2012–2013 |
| BEIGEL KURT D | 1 | 2012 |
| BISSEY LUCIEN J | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 140 | 1991–2021 |