Inventor
CHEE HIONG CHEW
Inventor
MY
Overview
Patents· 53 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1036%
H01LSemiconductor devices35%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
H05KPrinted circuits6%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form2%
H01RElectrically-conductive connections2%
H10DInorganic electric semiconductor devices2%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems1%
Y10TTechnical subjects covered by former us classification1%
C04BLime, magnesia1%
PatentTitleYear
12,525,519Semiconductor package with guide pin202612,513,870Power module202512,444,609Silicon-on-insulator die support structures and related methods202512,424,522Leadless semiconductor packages, leadframes therefor, and methods of making202512,402,264Stacked power terminals in a power electronics module202512,394,692Power circuit module202512,374,555Die sidewall coatings and related methods202512,374,554Semiconductor packages with die including cavities and related methods202512,362,266Low stress asymmetric dual side module202512,355,009Low stress asymmetric dual side module202512,347,755Low stress asymmetric dual side module202512,347,813Semiconductor package and related methods202512,347,812Low stress asymmetric dual side module202512,300,558Substrates and related methods202512,283,562Clip design and method of controlling clip position202512,243,810Semiconductor package with wettable flank and related methods202512,211,775Multiple substrate package systems and related methods202512,176,272Semiconductor package with wettable flank202412,040,192Die sidewall coatings and related methods202412,033,904Semiconductor package system and related methods202411,955,412Low stress asymmetric dual side module202411,948,870Low stress asymmetric dual side module202411,908,699Semiconductor packages with die including cavities202411,908,840Low stress asymmetric dual side module202411,901,184Backmetal removal methods202411,894,234Semiconductor packages with die support structure for thin die202411,894,347Low stress asymmetric dual side module202411,830,856Semiconductor package and related methods202311,804,421Connecting clip design for pressure sintering202311,791,288Reinforced semiconductor die and related methods202311,710,687Semiconductor package with guide pin202311,672,087Semiconductor package202311,569,140Semiconductor package with elastic coupler and related methods202311,562,938Spacer with pattern layout for dual side cooling power module202311,557,530Semiconductor devices and methods of making the same202311,532,539Semiconductor package with wettable flank202211,508,679Polymer resin and compression mold chip scale package202211,482,468Power module package casing with protrusion supports202211,469,163Low stress asymmetric dual side module202211,462,515Low stress asymmetric dual side module202211,452,225Fin frame assemblies202211,437,304Substrate structures and methods of manufacture202211,404,277Die sidewall coatings and related methods202211,404,276Semiconductor packages with thin die and related methods202211,374,373Press-fit pin for semiconductor packages and related methods202211,373,939Quad leadframe packages and related methods202211,361,970Silicon-on-insulator die support structures and related methods202211,348,878Reinforced semiconductor die and related methods202211,348,796Backmetal removal methods202211,342,189Semiconductor packages with die including cavities and related methods202211,342,237Semiconductor package system and related methods202211,272,625Method for forming a semiconductor package202211,217,506Semiconductor device assemblies including low-stress spacer2022Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2022–2026Patents assigned to SEMICONDUCTOR COMPONENTS IND LLC (53)· patent assignee history
2022–2026Based in MY· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEMICONDUCTOR COMPONENTS IND LLC | 53 | 2022–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| MY | 53 | 2022–2026 |