Inventor
Koushik Chakraborty
Inventor
Logan, UT, US
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H04Wprimary
H04WWireless communication networks24%
G06FElectric digital data processing22%
H04LTransmission of digital information, e.g. telegraphic communication20%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%
H04BTransmission11%
C08GMacromolecular compounds obtained otherwise than by reactions only involving unsaturated carbon-to-carbon bonds2%
C08JWorking-up2%
C08KUse of inorganic or non-macromolecular organic substances as compounding ingredients2%
C08LCompositions of macromolecular compounds2%
H04JMultiplex communication2%
PatentTitleYear
11,015,022Phosphorus based co-monomer for polyamides202111,005,576Signaling mechanism to enable local operation for multi-antenna wireless communication systems202111,006,360Multi-beam physical downlink control channel (PDCCH) monitoring during connected mode discontinuous reception (CDRX) operation202110,992,350Cross-sub-band quasi co-location signaling202110,993,252Scheduling request multiplexing based on reliability and latency objectives202110,993,256Variable-length transmission schemes202110,945,214Uplink power control202110,912,012Initial network access for downlink unlicensed deployment202110,904,843Techniques and apparatuses for handling power state transitions of a beamforming apparatus202110,904,773Beam management techniques in millimeter wave systems202110,893,540Random access channel procedures with multiple carriers202110,193,827Hot carrier injection tolerant network on chip router architecture201910,057,281Runtime detection of a bandwidth denial attack from a rogue interconnect20189,727,342'Error resilient pipeline'20179,652,611'Mitigating a compromised network on chip'20179,396,302'Global router using graphics processing unit'20169,344,358'Aging-aware routing for NoCs'20169,213,577'Sustainable differentially reliable architecture for dark silicon'20159,063,667'Dynamic memory relocation'20159,058,070'Predicting timing violations'20158,874,941'Apparatus and method for designing an architecturally homogeneous power-performance heterogeneous multicore processor using simulated annealing optimization'20148,549,456'System and method for circuit design floorplanning'20137,962,774'Over-provisioned multicore processor'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Based in Madison, WI, US· patent location history
2013–2018Patents assigned to UNIV UTAH STATE (10)· patent assignee history
2013–2019Patents assigned to CHAKRABORTY KOUSHIK (9)· patent assignee history
2013–2019Patents assigned to ROY SANGHAMITRA (9)· patent assignee history
2013–2019Based in Logan, UT, US· patent location history
2015–2019Patents assigned to ANCAJAS DEAN MICHAEL (4)· patent assignee history
2021Patents assigned to QUALCOMM INC (10)· patent assignee history
2021Based in San Diego, CA, US· patent location history
2021Based in Vadodara, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 10 | 2021 |
| UNIV UTAH STATE | 10 | 2013–2018 |
| CHAKRABORTY KOUSHIKself | 9 | 2013–2019 |
| ROY SANGHAMITRA | 9 | 2013–2019 |
| ANCAJAS DEAN MICHAEL | 4 | 2015–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Logan, UT, US | 11 | 2013–2019 |
| San Diego, California, US | 10 | 2021 |
| Vadodara, IN | 1 | 2021 |
| Madison, WI, US | 1 | 2011 |