Inventor
Lionel Chien Hui Tay
Inventor
Singapore, SG
Overview
Patents· 110 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1059%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1022%
H01LSemiconductor devices13%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation3%
H10DInorganic electric semiconductor devices3%
H04RLoudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers1%
PatentTitleYear
10,651,139Semiconductor device and method of forming wafer level ground plane and power ring2020RE047923Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps20209,922,955'Semiconductor device and method of forming package-on-package structure electrically interconnected through TSV in WLCSP'20189,666,540'Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die'20179,589,876'Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection'20179,525,080'Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device'20169,397,236'Optical semiconductor device having pre-molded leadframe with window and method therefor'20169,390,991'Semiconductor device and method of forming wafer level ground plane and power ring'20169,337,161'Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof'20169,257,357'Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die'20169,252,075'Semiconductor device and method of forming a conductive via-in-via structure'20169,202,777'Semiconductor package system with cut multiple lead pads'20159,142,531'Integrated circuit packaging system with plated leads and method of manufacture thereof'20159,142,514'Semiconductor device and method of forming wafer level die integration'20159,129,971'Semiconductor device with bump interconnection'20159,076,737'Integrated circuit packaging system with bumps and method of manufacture thereof'20159,059,074'Integrated circuit package system with planar interconnect'20158,957,515'Integrated circuit package system with array of external interconnects'20158,941,219'Etched recess package on package system'20158,940,636'Through hole vias at saw streets including protrusions or recesses for interconnection'20158,937,393'Integrated circuit package system with device cavity'20158,921,983'Semiconductor package and method of forming similar structure for top and bottom bonding pads'20148,884,418'Semiconductor device and method of forming PIP with inner known good die interconnected with conductive bumps'20148,866,248'Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device'20148,810,017'Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof'20148,729,693'Integrated circuit packaging system with a leaded package and method of manufacture thereof'20148,722,457'System and apparatus for wafer level integration of components'20148,692,377'Integrated circuit packaging system with plated leads and method of manufacture thereof'20148,664,038'Integrated circuit packaging system with stacked paddle and method of manufacture thereof'20148,643,157'Integrated circuit package system having perimeter paddle'20148,592,252'Semiconductor device and method of forming through hole vias in die extension region around periphery of die'20138,586,422'Optical semiconductor device having pre-molded leadframe with window and method therefor'20138,546,189'Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection'20138,536,690'Integrated circuit packaging system with cap layer and method of manufacture thereof'20138,518,749'Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die'20138,513,801'Integrated circuit package system'20138,502,376'Wirebondless wafer level package with plated bumps and interconnects'20138,502,371'Integrated circuit package system with extended corner leads'20138,493,748'Packaging system with hollow package and method for the same'20138,420,447'Integrated circuit packaging system with flipchip leadframe and method of manufacture thereof'20138,421,198'Integrated circuit package system with external interconnects at high density'20138,399,991'Semiconductor device and method of forming through hole vias in die extension region around periphery of die'20138,389,332'Integrated circuit packaging system with isolated pads and method of manufacture thereof'20138,362,601'Wire-on-lead package system having leadfingers positioned between paddle extensions and method of manufacture thereof'20138,354,742'Method and apparatus for a package having multiple stacked die'20138,344,495'Integrated circuit packaging system with interconnect and method of manufacture thereof'20138,304,869'Fan-in interposer on lead frame for an integrated circuit package on package system'20128,283,209'Semiconductor device and method of forming PiP with inner known good die interconnected with conductive bumps'20128,283,250'Semiconductor device and method of forming a conductive via-in-via structure'20128,278,148'Integrated circuit package system with leads separated from a die paddle'20128,273,602'Integrated circuit package system with integration port'20128,269,324'Integrated circuit package system with chip on lead'20128,258,614'Integrated circuit package system with package integration'20128,252,666'Semiconductor device and method of forming through hole vias in die extension region around periphery of die'20128,252,634'Integrated circuit packaging system with a leadframe having radial-segments and method of manufacture thereof'20128,241,954'Wafer level die integration and method'20128,216,883'Method for manufacturing semiconductor package system with die support pad'20128,212,342'Integrated circuit package system with removable backing element having plated terminal leads and method of manufacture thereof'20128,203,214'Integrated circuit package in package system with adhesiveless package attach'20128,203,220'Integrated circuit package system with multiple device units and method for manufacturing thereof'20128,174,098'Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via'20128,148,825'Integrated circuit package system with leadfinger'20128,148,208'Integrated circuit package system with leaded package and method for manufacturing thereof'20128,138,027'Optical semiconductor device having pre-molded leadframe with window and method therefor'20128,134,242'Integrated circuit package system with concave terminal'20128,134,227'Stacked integrated circuit package system with conductive spacer'20128,120,150'Integrated circuit package system with dual connectivity'20128,115,287'Integrated circuit packaging system with dual row lead-frame having top and bottom terminals and method of manufacture thereof'20128,115,305'Integrated circuit package system with thin profile'20128,106,502'Integrated circuit packaging system with plated pad and method of manufacture thereof'20128,097,943'Semiconductor device and method of forming wafer level ground plane and power ring'20128,072,047'Integrated circuit package system with shield and tie bar'20118,072,079'Through hole vias at saw streets including protrusions or recesses for interconnection'20118,043,894'Integrated circuit package system with redistribution layer'20118,039,302'Semiconductor package and method of forming similar structure for top and bottom bonding pads'20118,035,207'Stackable integrated circuit package system with recess'20118,022,539'Integrated circuit packaging system with increased connectivity and method of manufacture thereof'20117,998,790'Integrated circuit packaging system with isolated pads and method of manufacture thereof'20117,977,779'Mountable integrated circuit package-in-package system'20117,977,782'Integrated circuit package system with dual connectivity'20117,977,778'Integrated circuit package system with interference-fit feature'20117,977,780'Multi-layer package-on-package system'20117,964,450'Wirebondless wafer level package with plated bumps and interconnects'20117,960,815'Leadframe design for QFN package with top terminal leads'20117,932,130'Method for forming an etched recess package on package system'20117,919,850'Integrated circuit packaging system with exposed terminal interconnects and method of manufacturing thereof'20117,919,848'Integrated circuit package system with multiple devices'20117,915,724'Integrated circuit packaging system with base structure device'20117,915,716'Integrated circuit package system with leadframe array'20117,911,067'Semiconductor package system with die support pad'20117,911,040'Integrated circuit package with improved connections'20117,888,181'Method of forming a wafer level package with RDL interconnection over encapsulant between bump and semiconductor die'20117,871,862'Ball grid array package stacking system'20117,863,732'Ball grid array package system'20117,863,102'Integrated circuit package system with external interconnects within a die platform'20117,855,444'Mountable integrated circuit package system with substrate'20107,851,246'Semiconductor device with optical sensor and method of forming interconnect structure on front and backside of the device'20107,842,607'Semiconductor device and method of providing a thermal dissipation path through RDL and conductive via'20107,838,395'Semiconductor wafer level interconnect package utilizing conductive ring and pad for separate voltage supplies and method of making the same'20107,790,576'Semiconductor device and method of forming through hole vias in die extension region around periphery of die'20107,785,929'Mountable integrated circuit package system with exposed external interconnects'20107,777,354'Integrated circuit package system with leaded package'20107,763,493'Integrated circuit package system with top and bottom terminals'20107,759,806'Integrated circuit package system with multiple device units'20107,750,451'Multi-chip package system with multiple substrates'20107,732,901'Integrated circuit package system with isloated leads'20107,723,840'Integrated circuit package system with contoured die'20107,714,419'Integrated circuit package system with shielding'20107,582,957'Integrated circuit package system with encapsulation lock'20097,517,733'Leadframe design for QFN package with top terminal leads'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2020Patents assigned to STATS CHIPPAC LTD (105)· patent assignee history
2009–2020Based in Singapore, SG· patent location history
2011–2018Patents assigned to TAY LIONEL CHIEN HUI (66)· patent assignee history
2011–2015Patents assigned to CAMACHO ZIGMUND RAMIREZ (42)· patent assignee history
2011–2015Patents assigned to BATHAN HENRY DESCALZO (27)· patent assignee history
2011–2018Patents assigned to CAMACHO ZIGMUND R (23)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| STATS CHIPPAC LTD | 105 | 2009–2020 |
| TAY LIONEL CHIEN HUIself | 66 | 2011–2018 |
| CAMACHO ZIGMUND RAMIREZ | 42 | 2011–2015 |
| BATHAN HENRY DESCALZO | 27 | 2011–2015 |
| CAMACHO ZIGMUND R | 23 | 2011–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Singapore, SG | 110 | 2009–2020 |