Inventor
CHIA-HONG JAN
Inventor
US
Overview
Patents· 26 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices35%
H10DInorganic electric semiconductor devices35%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H10NElectric solid-state devices not otherwise provided for2%
PatentTitleYear
12,520,578Methods of integrating multiple gate dielectric transistors on a tri-gate (finfet) process202612,389,626High-voltage transistor with self-aligned isolation202512,317,585Adjacent gate-all-around integrated circuit structures having non-merged epitaxial source or drain regions202512,191,207Non-planar I/O and logic semiconductor devices having different workfunction on common substrate202512,136,628High voltage three-dimensional devices having dielectric liners202411,967,615Dual threshold voltage (VT) channel devices and their methods of fabrication202411,881,486High voltage three-dimensional devices having dielectric liners202411,830,818Semiconductor device having metal interconnects with different thicknesses202311,823,954Non-planar I/O and logic semiconductor devices having different workfunction on common substrate202311,824,002Variable pitch and stack height for high performance interconnects202311,764,260Dielectric and isolation lower fin material for fin-based electronics202311,737,362Harvesting energy in an integrated circuit using the seebeck effect202311,695,008Methods of integrating multiple gate dielectric transistors on a tri-gate (FINFET) process202311,688,792Dual self-aligned gate endcap (SAGE) architectures202311,610,917High voltage three-dimensional devices having dielectric liners202311,605,632Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls202311,563,000Gate endcap architectures having relatively short vertical stack202311,562,999Cost effective precision resistor using blocked DEPOP method in self-aligned gate endcap (SAGE) architecture202311,335,601Non-planar I/O and logic semiconductor devices having different workfunction on common substrate202211,329,138Self-aligned gate endcap (SAGE) architecture having endcap plugs202211,276,760Non-planar semiconductor device having omega-fin with doped sub-fin region and method to fabricate same202211,264,329Semiconductor device having metal interconnects with different thicknesses202211,251,201High voltage three-dimensional devices having dielectric liners202211,217,582Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls202211,205,708Dual self-aligned gate endcap (SAGE) architectures202111,139,370Dielectric and isolation lower fin material for fin-based electronics2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (25)· patent assignee history
2021–2026Based in US· patent location history
2023Patents assigned to TAHOE RES LTD (1)· patent assignee history
2025Patents assigned to INTEL CORPROATION (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 25 | 2021–2026 |
| INTEL CORPROATION | 1 | 2025 |
| TAHOE RES LTD | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 26 | 2021–2026 |